Stress testing a processor memory with a link stack

Patent metadata

Field	Value
Publication number	US-10540249-B2
Application number	US-201715804512-A
Country	US
Kind code	B2
Filing date	Nov 6, 2017
Priority date	Mar 14, 2017
Publication date	Jan 21, 2020
Grant date	Jan 21, 2020

Abstract

A processor memory is stress tested with a variable link stack depth using link stack test segments with non-naturally aligned data boundaries. Link stack test segments are interspersed into test code of a processor memory tests to change the link stack depth without changing results of the test code. The link stack test segments are the same structure as the segments of the test code and have non-naturally aligned boundaries. The link stack test segments include branch to target, push/pop, push and pop segments. The depth of the link stack is varied independent of the memory test code by changing the number to branches in the branch to target segment and varying the number of the push/pop segments.

First claim

The invention claimed is:

1. An apparatus for testing a computer processor comprising:
a test case generator that allows a user to create test cases with test code for testing the computer processor;
a test case executor that replicates the test code and loads the replicated test code into non-naturally aligned segments of consecutive memory locations on the computer processor;
wherein the test case executor further adds link stack test segments interspersed in the test code in non-naturally aligned segments that vary the depth of a link stack without affecting the test code results; and
wherein the computer processor executes the test code with the link stack test segments to test the memory of the computer processor with varying depth of the link stack independent of the test code.

2. The apparatus of claim 1 wherein the replicated test code in the non-naturally aligned segments comprise sub-segments of test code that include word, double word and quad word sub-segments.

3. The apparatus of claim 1 wherein the replicated test code in the non-naturally aligned segments have seven words of test code with one single word sub-segment, one double word sub-segment and one quad word sub-segment.

4. The apparatus of claim 1 wherein the link stack test segments comprise:
a branch to target segment that comprises a plurality of branches to sub-routines of test code; and
a push/pop segment that branches to a push segment, branches to a test segment, and then branches to a pop segment.

5. The apparatus of claim 4 wherein the push segment pushes a copy of a link register to a link register save area within the push/pop segment.

6. The apparatus of claim 5 wherein the pop segment loads the copy of the link register in the push/pop segment and stores it to the link register and returns execution via the link register.

7. The apparatus of claim 4 wherein the push segment and the pop segment are located outside the test code and used by a plurality of test cases.

8. The apparatus of claim 1 wherein the test case executor further modifies a last instruction of one or more test code segments to change a branch location consistent with subroutine calls in the push/pop segment and the branch to target segment.

9. An apparatus for testing a computer processor comprising:
a test case generator that allows a user to create test cases with test code for testing the computer processor;
a test case executor that replicates the test code and loads the replicated test code into non-naturally aligned segments of consecutive memory locations on the computer processor wherein non-naturally aligned means ends of the segments when placed end-to-end with another segment do not fall on a natural boundary that is a number of the form 2 n ;
wherein the test case executor further adds link stack test segments interspersed in the test code in non-naturally aligned segments that vary the depth of a link stack without affecting the test code results; and
wherein the computer processor executes the test code with the link stack test segments to test the memory of the computer processor with varying depth of the link stack independent of the test code;
wherein the replicated test code in the non-naturally aligned segments comprise sub-segments of test code that include word, double word and quad word sub-segments.

10. The apparatus of claim 9 wherein the replicated test code in the non-naturally aligned segments have seven words of test code with one single word sub-segment, one double word sub-segment and one quad word sub-segment.

11. The apparatus of claim 9 wherein the link stack test segments comprise:
a branch to target segment that comprises a plurality of branches to sub-routines of test code; and
a push/pop segment that branches to a push segment, branches to a test segment, and then branches to a pop segment.

12. The apparatus of claim 11 wherein the push segment pushes a copy of a link register to a link register save area within the push/pop segment.

13. The apparatus of claim 12 wherein the pop segment loads the copy of the link register in the push/pop segment and stores it to the link register and returns execution via the link register.

14. The apparatus of claim 11 wherein the push segment and the pop segment are located outside the test code and used by a plurality of test cases.

15. The apparatus of claim 9 wherein the test case executor further modifies a last instruction of one or more test code segments to change a branch location consistent with subroutine calls in the push/pop segment and the branch to target segment.

Assignees

• IBM

Inventors

• Dusanapudi Manoj
• Kapoor Shakti

Classifications

• G06F11/263 Primary

  Generation of test inputs, e.g. test vectors, patterns or sequences {; with adaptation of the tested hardware for testability with external testers} · CPC title

• G06F11/008

  Reliability or availability analysis · CPC title