Method, system, and apparatus for stress testing memory translation tables

Patent metadata

Field	Value
Publication number	US-10521355-B2
Application number	US-201715843595-A
Country	US
Kind code	B2
Filing date	Dec 15, 2017
Priority date	Dec 15, 2017
Publication date	Dec 31, 2019
Grant date	Dec 31, 2019

Abstract

Disclosed is a system, method and/or computer product that includes generating translation requests that are identical but have different expected results, transmitting the translation requests from a MMU tester to a non-core MMU disposed on a processor chip, where the non-core MMU is external to a processing core of the processor chip, and where the MMU tester is disposed on a computing component external to the processor chip. The method also includes receiving memory translation results from the non-core MMU at the MMU tester, comparing the results to determine if there is a flaw in the non-core MMU.

First claim

The invention claimed is:

1. A method executed by a processor, the method comprising:
generating a first command table containing a first set of virtual memory addresses and a first set of physical memory addresses;
generating a page table based on the first command table, wherein the page table enables a non-core memory management unit (“MMU”) to execute a first set of translation requests that were generated based on the virtual and physical memory addresses contained in the first command table by translating the first set of virtual memory address into the first set of physical memory addresses;
polling a first flag to determine if the non-core MMU has completed the first set of translation requests; and
invalidating the page table on a condition that the first flag indicates that the first set of translation requests have been completed by the non-core MMU.

2. The method of claim 1 , further comprising setting the first flag to indicate that the page table has been invalidated.

3. The method of claim 1 , wherein the first flag is set by a MMU tester after a first set of translation results are received by the MMU tester.

4. The method of claim 3 , wherein the processor and the MMU tester are not in direct communication.

5. The method of claim 1 , wherein no processing core in the processor can transmit translation requests to the non-core MMU.

6. The method of claim 1 , wherein non-core hardware is disposed in the processor, wherein the non-core hardware is communicatively coupled to the non-core MMU in the processor chip for performing memory translations.

7. The method of claim 1 further comprising generating a second command table containing a second set of virtual memory addresses and a second set of physical memory addresses.

8. The method of claim 7 , wherein the first and second sets of virtual memory addresses are identical and the first and second sets of physical memory addresses are different.

9. The method of claim 7 further comprising updating the page table based on the second command table to enable the non-core MMU to execute a second set of translation requests that were generated based on the virtual and physical memory addresses contained in the second command table by translating the second set of virtual memory address into the second set of physical memory addresses.

10. The method of claim 9 , further comprising:
polling a second flag to determine if the non-core MMU has completed the second set of translation requests;
invalidating the updated page table on a condition that the second flag indicates that the second set of translation results have been received; and
resetting the second flag.

11. A method executed by a memory management unit (“MMU”) tester, the method comprising:
polling a first flag to determine whether a non-core MMU disposed on a processor chip is ready to receive a first set of translation requests that include a first set of virtual memory addresses;
on a condition that the first flag indicates that the non-core MMU is ready to receive the first set of translation requests, transmitting the first set of translation requests from the MMU tester to a non-core MMU, wherein the first set of translation requests are based on a first command table; and
receiving, at the MMU tester, a first set of memory translation results from the non-core MMU in response to the first set of translation requests; and
comparing the first set of translation results to a previously received set of translation results and halting execution of the MMU tester on a condition that the first set of translation results match the previously received set of translation results.

12. The method of claim 11 , wherein the non-core MMU is external to a processing core of the processor chip.

13. The method of claim 11 , wherein the MMU tester is disposed on a computing component external to the processor chip.

14. The method of claim 13 , wherein the computing component is a field-programmable gate array (FPGA), the method further comprising:
executing the MMU tester using circuit elements in the FPGA.

15. The method of claim 14 , wherein transmitting translation requests from a MMU tester to a non-core MMU comprises:
transmitting data between the FPGA and the processor chip using a PCIe link.

16. The method of claim 11 , further comprising setting the first flag to indicate that the first set translation results have been received.

17. The method of claim 11 , further comprising:
transmitting a second set of translation requests from the MMU tester to the non-core MMU, wherein the second set of translation requests are based on a second command table;
receiving a second set of translation results from the non-core MMU at the MMU tester; and
comparing the second set of memory translation results with a previously received set of translation results, and halting execution of the MMU tester on a condition that the first set of translation results match the previously received set of translation results.

18. The method of claim 17 , further comprising setting the first flag to indicate that the second set translation results have been received.

19. A system, comprising:
a computer processor; and
a memory containing a computer program that, when executed by the computer processor, performs an operation in a simulated computing environment, the operation comprising:
simulating a non-core MMU in a simulated processor chip, wherein the non-core MMU is external to a processing core of the simulated processor chip;
simulating a MMU tester in a simulated computing component external to the processor chip, wherein the MMU tester is configured to generate a first set of translation requests based on a first command table containing a first set of virtual memory addresses and a first set of physical memory addresses and a second set of translation requests based on a second command table containing a second set of virtual memory addresses and a second set of physical memory addresses, wherein the first and second sets of virtual memory addresses are identical and the first and second physical memory addresses are different;
simulating a communication link between the simulated processor chip and the simulated computing component;
simulating a process for testing the non-core MMU comprising:
generating the first command table containing the first set of virtual memory addresses and the first set of physical memory addresses;
generating a page table based on the first command table, wherein the page table enables the non-core MMU to execute the first set of translation requests that were generated based on the virtual and physical memory addresses contained in the first command table by translating the first set of virtual memory address into the first set of physical memory addresses;
polling a first flag to determine if the non-core MMU has completed the first set of translation requests; and
invalidating the page table on a condition that the first flag indicates that the first set of translation requests have been completed by the non-core MMU.

20. The system of claim 19 , wherein the operation further comprises:
polling a second flag to determine whether the non-core MMU is ready to receive the first set of translation requests that include the first set of virtual memory addresses;
on a condition that the second flag indicates that the non-core MMU is ready to receive the first set of translation requests, transmitting the first set of translation requests from the MMU tester to t

Assignees

• IBM

Inventors

• Dusanapudi Manoj
• Kapoor Shakti
• Wu Nelson

Classifications

• G06F12/145

  the protection being virtual, e.g. for virtual blocks or segments before a translation mechanism · CPC title

• G06F12/1009 Primary

  using page tables, e.g. page table structures · CPC title

• G06F2212/654

  Look-ahead translation · CPC title

• G06F2212/1008

  Correctness of operation, e.g. memory ordering · CPC title

• G06F12/1027

  using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB] · CPC title