Test case generation for a hardware state space

Patent metadata

Field	Value
Publication number	US-2021042202-A1
Application number	US-201916537516-A
Country	US
Kind code	A1
Filing date	Aug 9, 2019
Priority date	Aug 9, 2019
Publication date	Feb 11, 2021
Grant date	—

Abstract

Test case generation for a hardware state space including: identifying, from a first test case comprising a first plurality of test operations executed by a processor comprising a first configuration, a test operation causing an invalid result; determining a functional path associated with the test operation; generating a second plurality of test operations based on the functional path; generating a processor state by executing, by the processor comprising a second configuration, a subset of the first plurality of test operations comprising the determined test operation; and generate a second test case comprising the second plurality of test operations configured for execution based on the processor state.

First claim

What is claimed is:

1 . A method of test case generation for a hardware state space, the method comprising:
identifying, from a first test case comprising a first plurality of test operations executed by a processor comprising a first configuration, a test operation causing an invalid result; determining a functional path associated with the test operation; generating a second plurality of test operations based on the functional path; generating a processor state by executing, by the processor comprising a second configuration, a subset of the first plurality of test operations comprising the determined test operation; and generate a second test case comprising the second plurality of test operations configured for execution based on the processor state.

2 . The method of claim 1 , wherein generating the second plurality of test operations comprises:
selecting a test case template associated with the functional path; and generating, based on the test case template, the second plurality of test operations.

3 . The method of claim 2 , wherein generating, based on the test case template, the second plurality of test operations comprises generating, based on the test case template and a seed value, the second plurality of test operations, and the method further comprises generating, based on the test case template and another seed value, a third test case comprising a third plurality of test operations configured for execution based on the processor state.

4 . The method of claim 2 , further comprising:
selecting another test case template associated with the functional area; and generating, based on the other test case template, a third test case comprising a third plurality of test operations configured for execution based on the processor state.

5 . The method of claim 1 , further comprising generating, based on a test case template and a seed value, the first test case comprising the first plurality of test operations.

6 . The method of claim 5 , wherein the subset of the first plurality of test operations is based on the test case template and the seed value.

7 . The method of claim 1 , further comprising executing, by the processor comprising the second configuration, the second plurality of test operations.

8 . An apparatus for test case generation for a hardware state space, the apparatus comprising a computer processor, a computer memory operatively coupled to the computer processor, the computer memory having disposed within it computer program instructions that, when executed by the computer processor, cause the apparatus to carry out the steps of:
identifying, from a first test case comprising a first plurality of test operations executed by a processor comprising a first configuration, a test operation causing an invalid result; determining a functional path associated with the test operation; generating a second plurality of test operations based on the functional path; generate a processor state by executing, by the processor comprising a second configuration, a subset of the first plurality of test operations comprising the determined test operation; and generate a second test case comprising the second plurality of test operations configured for execution based on the processor state.

9 . The apparatus of claim 8 , wherein generating the second plurality of test operations comprises:
selecting a test case template associated with the functional path; and generating, based on the test case template, the second plurality of test operations.

10 . The apparatus of claim 9 , wherein generating, based on the test case template, the second plurality of test operations comprises generating, based on the test case template and a seed value, the second plurality of test operations, and the steps further comprise generating, based on the test case template and another seed value, a third test case comprising a third plurality of test operations configured for execution based on the processor state.

11 . The apparatus of claim 9 , wherein the steps further comprise:
selecting another test case template associated with the functional area; and generating, based on the other test case template, a third test case comprising a third plurality of test operations configured for execution based on the processor state.

12 . The apparatus of claim 8 , wherein the steps further comprise generating, based on a test case template and a seed value, the first test case comprising the first plurality of test operations.

13 . The apparatus of claim 12 , wherein the subset of the first plurality of test operations is based on the test case template and the seed value.

14 . The apparatus of claim 8 , wherein the steps further comprise executing, by the processor comprising the second configuration, the second plurality of test operations.

15 . A computer program product for test case generation for a hardware state space, the computer program product disposed upon a computer readable medium, the computer program product comprising computer program instructions that, when executed, cause a computer to carry out the steps of:
identifying, from a first test case comprising a first plurality of test operations executed by a processor comprising a first configuration, a test operation causing an invalid result; determining a functional path associated with the test operation; generating a second plurality of test operations based on the functional path; generate a processor state by executing, by the processor comprising a second configuration, a subset of the first plurality of test operations comprising the determined test operation; and generate a second test case comprising the second plurality of test operations configured for execution based on the processor state.

16 . The computer program product of claim 15 , wherein generating the second plurality of test operations comprises:
selecting a test case template associated with the functional path; and generating, based on the test case template, the second plurality of test operations.

17 . The computer program product of claim 16 , wherein generating, based on the test case template, the second plurality of test operations comprises generating, based on the test case template and a seed value, the second plurality of test operations, and the steps further comprise generating, based on the test case template and another seed value, a third test case comprising a third plurality of test operations configured for execution based on the processor state.

18 . The computer program product of claim 16 , wherein the steps further comprise:
selecting another test case template associated with the functional area; and generating, based on the other test case template, a third test case comprising a third plurality of test operations configured for execution based on the processor state.

19 . The computer program product of claim 15 , wherein the steps further comprise generating, based on a test case template and a seed value, the first test case comprising the first plurality of test operations.

20 . The computer program product of claim 19 , wherein the subset of the first plurality of test operations is based on the test case template and the seed value.

Assignees

• IBM

Inventors

• Kadiyala Madhusudan
• Adiga Narasimha R
• Dusanapudi Manoj

Classifications

• G06F11/263 Primary

  Generation of test inputs, e.g. test vectors, patterns or sequences {; with adaptation of the tested hardware for testability with external testers} · CPC title

• G06F11/273

  Tester hardware, i.e. output processing circuits {(G06F11/263 takes precedence)} · CPC title