List insertion in test segments with non-naturally aligned data boundaries

Patent metadata

Field	Value
Publication number	US-10438682-B2
Application number	US-201715850201-A
Country	US
Kind code	B2
Filing date	Dec 21, 2017
Priority date	Dec 21, 2017
Publication date	Oct 8, 2019
Grant date	Oct 8, 2019

Abstract

A processor memory is stress tested with a variable list insertion depth using list insertion test segments with non-naturally aligned data boundaries. List insertion test segments are interspersed into test code of a processor memory tests to change the list insertion depth without changing results of the test code. The list insertion test segments are the same structure as the segments of the test code and have non-naturally aligned boundaries. The list insertion test segments include list insertion segments and load/store segments. The list insertion segments locate a current memory location using a fixed segment at a known location. The load/store segments load and store list elements in memory.

First claim

The invention claimed is:

1. A computer-implemented method executed by at least one processor for testing a computer processor comprising:
providing test code in a plurality of segments with non-naturally aligned boundaries;
interspersing a plurality of list insertion test segments with non-naturally aligned boundaries into the test code segments by:
providing a plurality of list insertion segments;
providing a plurality of load/store segments; and
wherein each list insertion segment branches to a fixed segment that determines a first list element location and includes a second list element location, and
wherein each load/store segment loads a list element stored in the second list element location and stores the list element in the first list element location; and

executing the test code with the interspersed list insertion test segments to insert a list element into at least one of a plurality of list element locations using a fixed segment stored at a fixed location on the computer processor.

2. The method of claim 1 , further comprising determining the first list element location by:
storing an address to a next consecutive memory location contained in a link register of the computer processor into one of a plurality of general purpose registers of the computer processor;
branching to the fixed segment and storing an address to the first list element location contained in the link register into a second of the plurality of general purpose registers;
calculating an address to a return memory location consecutive to the first list element location and storing the return memory location to the link register; and
branching to the return memory location and restoring the address to the next consecutive memory location to the link register.

3. The method of claim 2 , further comprising inserting the list element in the first list element location by:
loading from memory a list element stored in the second list element location and storing the list element into one of the plurality of general purpose registers;
storing the list element into the first list element location; and
storing the address to the first list element location into the second list element location.

4. The method of claim 3 , further comprising, after storing the list element into one of the plurality of general purpose registers, prohibiting write access to the second list element location.

5. The method of claim 4 , further comprising:
determining whether another process attempts to write to the second list element location after write access has been prohibited;
if another process has attempted to write the list element after write access has been prohibited, performing the steps of loading from memory the list element, prohibiting write access to the second list element location, and determining whether another process attempts to write to the second list element location until no process attempts to write to the second list element location after write access has been prohibited; and
before storing the address to the first list element location into the second list element location, enabling write access to the second list element location.

6. The method of claim 1 , further comprising providing at least one checking segment.

7. The method of claim 6 , further comprising successively checking each list element inserted into memory to confirm that the list insertion segment and load/store segments executed correctly.

8. The method of claim 1 , wherein the fixed segment is located outside the test code and used by a plurality of test cases.

9. The method of claim 1 , wherein non-naturally aligned means ends of the segments when placed end-to-end with another segment do not fall on a natural boundary that is a number of the form 2n.

10. A computer-implemented method executed by at least one processor for testing a computer processor comprising:
providing test code in a plurality of segments with non-naturally aligned boundaries; interspersing a plurality of list insertion test segments that have non-naturally aligned boundaries into the test code segments comprising:
providing a plurality of list insertion segments;
providing a plurality of load/store segments;
wherein each list insertion segment branches to a fixed segment that determines a first list element location and that includes a second list element location, and wherein each load/store segment that loads a list element stored in the second list element location, stores the list element in the first list element location;
executing the test code with the interspersed list insertion test segments to insert a list element into at least one of a plurality of list element locations using a fixed segment stored at a fixed location on the computer processor; and
determining the second list element location by:
storing an address to a next consecutive memory location contained in a link register of the computer processor into one of a plurality of general purpose registers of the computer processor;
branching to the fixed segment and storing an address to the first list element location contained in the link register into a second of the plurality of general purpose registers;
calculating an address to a return memory location consecutive to the first list element location and storing the return memory location to the link register; and
branching to the return memory location, wherein after branching the link register contains an address a second list element location;
storing the address of the second list element location into the second of the plurality of general purpose register; and
restoring the address to the next consecutive memory location to the link register.

11. The method of claim 10 , further comprising:
loading from memory a list element stored in the second list element location and storing the list element into one of the plurality of general purpose registers;
storing the list element into the first list element location, wherein the list element is equal to zero;
prohibiting write access to the second list element location;
determining whether another process attempts to write to the second list element location after write access has been prohibited;
if another process has attempted to write to the list element after write access has been prohibited, performing the steps of loading from memory the list element, prohibiting write access to the second list element location, and determining whether another process attempts to write to the second list element location until no process attempts to write to the first list element location after write access has been prohibited; and
if no process has attempted to write to the second list element location after write access has been prohibited, enabling write access to the second list element location;
storing the address to the first list element location into the second list element location; initializing a counter at a high value;
decrementing the counter;
on a condition that the counter does not equal zero, retrieving data from a memory location, wherein an address for the memory location is stored in the second of the plurality of general purpose registers and storing the data in the second of the plurality of general purpose registers;
determining whether the data in the second of the plurality of general purpose registers greater than zero;
repeating the decrementing, retrieving, and determining steps until either
the data in the second of the plurality of general purpose registers is not greater than zero, or;
the counter equals equal zero; and

on a condition the counter equals zero, sending an interrupt to an interrupt handler,
wherein test cod

Assignees

• IBM

Inventors

• Dusanapudi Manoj
• Kapoor Shakti
• Wu Nelson

Classifications

• G11C29/36

  Data generation devices, e.g. data inverters · CPC title

• G11C29/06

  Acceleration testing · CPC title

• G11C29/50

  Marginal testing, e.g. race, voltage or current testing · CPC title

• G11C2029/4402

  Internal storage of test result, quality data, chip identification, repair information · CPC title

• G11C29/38 Primary

  Response verification devices · CPC title