Core pairing in multicore systems

Patent metadata

Field	Value
Publication number	US-10831620-B2
Application number	US-201615183044-A
Country	US
Kind code	B2
Filing date	Jun 15, 2016
Priority date	Jun 15, 2016
Publication date	Nov 10, 2020
Grant date	Nov 10, 2020

Abstract

A method, executed by a computer, includes pairing a first core with a second core to form a first core group, wherein each core of the group has a plurality of functional units, transferring instructions received by the first core to the second core for execution via a first inter-core communication bus, and executing the instructions on the second core. A computer system and computer program product corresponding to the above method are also disclosed herein.

First claim

What is claimed is:

1. A method comprising:
receiving, from an instruction cache of a first core of a processor and by a fetching unit of the first core, a set of undecoded instruction(s);
passing, by the fetching unit and to a decode unit of the first core, the set of undecoded instruction(s);
decoding, by the decode unit, the set of undecoded instruction(s) to obtain a set of decoded instruction(s), with the set of decoded instructions being in a form that is executable by the processor;
determining, by the decode unit, that a first decoded instruction(s) sub-set of the set of decoded instruction(s) is to be executed;
determining, by the decode unit, that a second decoded instruction(s) sub-set of the set of decoded instruction(s) is to be executed;
determining that a first critical path of execution requirement has been met, with the first critical path of execution requirement being that the first decoded instruction(s) sub-set and the second decoded instruction(s) sub-set are to be executed on separate cores of the processor;
determining, by a set of queue issuing unit(s), that the first decoded instruction(s) sub-set should be transferred from the first core of the processor to a second core of the processor based, at least in part, upon the first critical path of execution requirement being met;
responsive to the determination that the first decoded instruction(s) sub-set should be transferred from the first core to the second core, transferring, by the set of queue issuing unit(s), the first decoded instruction(s) sub-set from the first core to a set of functional unit(s) of the second core;
determining that a first portion of the first decoded instruction(s) sub-set can be executed by the set of functional unit(s) of the second core;
executing the first portion of the first decoded instruction(s) sub-set by the set of functional unit(s) of the second core;
determining that the set of functional unit(s) of the second core have reached a maximum execution capacity, with the maximum execution capacity being an upper limit of an amount of decoded instruction(s) that the set of functional unit(s) can execute at a given time;
responsive to the determination that the set of functional unit(s) of the second core have reached the maximum execution capacity, transferring, by the set of queue issuing unit(s), a remainder portion of the first decoded instruction(s) sub-set from the second core to the first core; and
responsive to transfer of the remainder portion of the first decoded instruction(s) sub-set, queuing the remainder portion of the first decoded instruction(s) sub-set for execution by the set of functional unit(s) of the first core so that the remainder portion of the first decoded instruction(s) sub-set can be executed at a point in time after the execution of the first portion of the first decoded instruction(s);
wherein:
the first decoded instruction(s) sub-set is entirely made up of the first portion and the remainder portion, the first portion being distinct from the remainder portion; and
the first core and the second core are both included in the same processor.

2. The method of claim 1 wherein the first decoded instruction(s) sub-set is transferred from the first core to the second core by an inter-core communication bus, with the inter-core communication bus being included in the same processor that includes the first core and the second core.

3. The method of claim 1 wherein the first decoded instruction(s) sub-set is transferred from the first core to the second core in order to avoid overtaxing the first core.

4. The method of claim 2 wherein the inter-core communication bus is structured, located and connected to provide two way communication as follows: (i) transfer instructions from the first core to the second core, and (ii) transfer execution status from the second core to the first core.

5. The method of claim 1 further comprising:
determining, by the set of queue issuing unit(s), that the second decoded instruction(s) sub-set should remain on the first core of the processor based, at least in part, upon the first critical path of execution requirement;
responsive to the determination that the second decoded instruction(s) sub-set should remain on the first core of the processor, executing the second decoded instruction(s) sub-set by the set of functional unit(s) of the first core; and
executing the remainder portion by the set of functional unit(s) of the first core.

Assignees

• IBM

Inventors

• Dusanapudi Manoj
• Jayaraman Prasanna
• Rao Rahul M

Classifications

• G06F9/3836 Primary

  Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution · CPC title

• G06F11/2043

  where the redundant components share a common memory address space · CPC title

• G06F11/0724

  in a multiprocessor or a multi-core unit (multiprocessors per se G06F15/80) · CPC title

• G06F11/2035

  without idle spare hardware · CPC title

• G06F9/46

  Multiprogramming arrangements · CPC title