Efficient testing of direct memory address translation

Patent metadata

Field	Value
Publication number	US-10489261-B2
Application number	US-201816145981-A
Country	US
Kind code	B2
Filing date	Sep 28, 2018
Priority date	Aug 12, 2017
Publication date	Nov 26, 2019
Grant date	Nov 26, 2019

Abstract

A circuit and method provide efficient stress testing of address translations in an integrated circuit such as a link processing unit. A random DMA mode (RDM) circuit provides a random input to index into a translation validation table (TVT) that is used to generate the real memory address. The RDM circuit allows testing all entries of the TVT, and thus all DMA modes, regardless of what bus agents are connected to the link processing unit. The RDM circuit may use a multiplexer to select between a runtime input and a random test input provided by the random bit generator. When the link processing unit is in a test mode a mode selection bit is asserted to select the random test input.

First claim

The invention claimed is:

1. An integrated circuit comprising:
a first translation table that includes a plurality of translation entries, wherein each of the plurality of translation entries contains translation information to translate direct memory access (DMA) addresses for one of a plurality of agents connected to the integrated circuit; and
a random DMA mode (RDM) circuit that randomly selects a translation control entry in the first translation table during a test mode.

2. The integrated circuit of claim 1 wherein the RDM circuit randomly selects from all the plurality of translation entries in the first translation table when there is only a single agent connected to the integrated circuit.

3. The integrated circuit of claim 1 wherein the RDM circuit comprises:
a random generator signal connected to a specified input of a multiplexer;
a select input of the multiplexer that selects the specified input; and
an output of the multiplexer that provides the random generator signal to the translation table during the test mode to randomly select an entry of the translation table during testing.

4. The integrated circuit of claim 1 wherein the first translation table is a translation validation table which contains translation validation entries for each of the plurality of agents that point to a translation control entry table and wherein the RDM circuit randomly selects a translation validation entry that points to a translation control entry in the translation control entry table.

5. The integrated circuit of claim 4 wherein the RDM randomly selects the translation control entry by randomly selecting a translation validation entry.

6. The integrated circuit of claim 5 wherein the information to translate DMA addresses in each entry of the first translation table comprises a translation table address, translation control entry tree depth, translation control entry table size and input/output page size.

7. The integrated circuit of claim 1 wherein the agents comprise a central processing unit and at least one graphics processing unit.

8. The integrated circuit of claim 1 wherein the integrated circuit is part of a link processing unit.

9. The integrated circuit of claim 8 wherein the link processing unit is fabricated on the integrated circuit with a central processing unit.

10. An integrated circuit comprising:
a first translation table that includes a plurality of translation entries, wherein each of the plurality of translation entries contains translation information to translate direct memory access (DMA) addresses for one of a plurality of agents connected to the integrated circuit;
a random DMA mode (RDM) circuit that randomly selects a translation control entry in the first translation table during a test mode; and
wherein the RDM circuit randomly selects from all the plurality of translation entries in the first translation table when there is at least one agent connected to the integrated circuit, wherein the at least one agent comprises a central processing unit and at least one graphics processing unit.

11. The integrated circuit of claim 10 wherein the RDM circuit comprises:
a random generator signal connected to a specified input of a multiplexer;
a select input of the multiplexer that selects the specified input; and
an output of the multiplexer that provides the random generator signal to the translation table during the test mode to randomly select an entry of the translation table during testing.

12. The integrated circuit of claim 10 wherein the first translation table is a translation validation table which contains translation validation entries for each of the plurality of agents that point to a translation control entry table and wherein the RDM circuit randomly selects a translation validation entry that points to a translation control entry in the translation control entry table.

13. The integrated circuit of claim 12 wherein the RDM randomly selects the translation control entry by randomly selecting a translation validation entry.

14. The integrated circuit of claim 13 wherein the information to translate DMA addresses in each entry of the first translation table comprises a translation table address, translation control entry tree depth, translation control entry table size and input/output page size.

15. The integrated circuit of claim 10 wherein the integrated circuit is part of a link processing unit.

16. The integrated circuit of claim 15 wherein the link processing unit is fabricated on the integrated circuit with a central processing unit.

Assignees

• IBM

Inventors

• Dusanapudi Manoj
• Kapoor Shakti
• Wu Nelson

Classifications

• G06F12/1081

  for peripheral access to main memory, e.g. direct memory access [DMA] · CPC title

• G06F11/2221 Primary

  to test input/output devices or peripheral units · CPC title

• G06F13/287

  Multiplexed DMA (G06F13/30 takes precedence) · CPC title

• G06F2212/1032

  Reliability improvement, data loss prevention, degraded operation etc · CPC title

• G06F11/26

  Functional testing · CPC title