Performance and reliability of processor store operation data transfers

Patent metadata

Field	Value
Publication number	US-2024028518-A1
Application number	US-202217869956-A
Country	US
Kind code	A1
Filing date	Jul 21, 2022
Priority date	Jul 21, 2022
Publication date	Jan 25, 2024
Grant date	—

Abstract

A processor includes a load and store unit (LSU) and a cache memory, and transfers data information from a store queue in the LSU to the cache memory. The cache memory requests an information packet from the LSU when the cache memory determines that an available entry exists in a store queue within the cache memory. The LSU acknowledges the request and transfers an information packet to the cache memory. The LSU anticipates that an additional available entry exists in the cache memory, transmits an additional acknowledgement to the cache memory, and transfers an additional information packet, before receiving an additional request from the cache memory. The cache memory stores the additional information packet if an additional available entry exists in the cache store queue. The cache memory rejects the additional information packet if no additional available entries exist in the cache store queue. The LSU must then retry the transfer of the additional information packet when the cache memory subsequently requests the additional information packet. The cache memory can set or reset a time delay in requesting a subsequent information packet based on several factors within the cache memory and the processor, including the number of available entries within the cache store queue. A corresponding method and computer program product are also disclosed.

First claim

What is claimed:

1 . A processor included within a central processing unit (CPU), the CPU included within a computer processor system, the CPU coupled to a memory, the processor comprising:
a load and store unit (LSU) including a control module and a store queue, the store queue including a plurality of entries for storing a plurality of information packets; a cache memory (L2 cache) coupled to the LSU, the L2 cache including a control module and a store queue, the store queue including a plurality of entries for storing a plurality of information packets; wherein the L2 cache determines that an available entry exists in the L2 cache store queue and transmits a request to the LSU to transfer an information packet; wherein the LSU transmits an acknowledgement from the L2 cache and transfers the information packet from the entry in the LSU store queue over a data bus coupled to the L2 cache; wherein the L2 cache receives the information packet from the LSU store queue and stores the information packet in the available entry in the L2 cache store queue; and wherein the LSU anticipates that the L2 cache store queue has an additional available entry, transmits an additional acknowledgement to the L2 cache, and transfers an additional information packet from an additional entry in the LSU store queue, before the L2 cache requests the additional information packet.

2 . The processor of claim 1 , wherein the L2 cache determines that an additional available entry exists in the L2 cache store queue, receives the additional information packet from the LSU store queue, and stores the additional information packet in the additional available entry within the L2 cache store queue; and
wherein the L2 cache delays transmitting a subsequent request to the LSU for a subsequent information packet to be transferred from the LSU, the subsequent request also serving as an acknowledgement to the LSU for storing the additional information packet in the L2 cache.

3 . The processor of claim 1 , wherein the L2 cache requests the information packet by transmitting a POP signal from the L2 cache control module along a control bus coupled to the LSU control module, and wherein the LSU acknowledges the request from the L2 cache by transmitting a PUSH signal from the LSU control module along the control bus coupled to the L2 cache control module.

4 . The processor of claim 2 , wherein the L2 cache control module determines the delay to request a subsequent information packet (subsequent request delay), and calculates the subsequent request delay based on the number of available entries within the L2 cache store queue.

5 . The processor of claim 4 , wherein the L2 cache control module calculates the subsequent request delay based on an average time to transfer the information packet from the LSU store queue to the L2 cache store queue.

6 . The processor of claim 4 , wherein the L2 cache control module sets and resets the subsequent request delay based on a threshold, wherein the threshold is the number of available entries in the L2 cache store queue;
wherein the L2 control module sets the subsequent request delay to a fixed time interval when the number of available entries in the L2 cache store queue is less than the threshold; and wherein the L2 cache control module resets the subsequent request delay to no time delay when the number of available entries in the L2 cache store queue is greater than or equal to the threshold.

7 . The processor of claim 1 , wherein the L2 cache determines that an additional available entry does not exist in the L2 cache store queue;
wherein the L2 cache control module transmits a BOUNCE signal along the control bus to the LSU control module to indicate that the additional information packet was rejected and not stored in the L2 cache store queue; and wherein the LSU must wait for a subsequent request from the L2 cache before retrying the transfer of the additional information packet.

8 . A method for improving the performance of store operation data information transfers within a computer processing system, the computer processing system including a processor and a memory, the processor including a cache memory and a load and store unit, the computer processing system further including a computer-readable storage medium having computer-usable program code embodied therein, the computer-usable program code configured to perform operations when executed by the processor, the method comprising:
storing an information packet within the load and store unit (LSU), the information packet to be transferred to the cache memory (L2 cache), the LSU including a store queue having a plurality of entries to store a plurality of information packets, the L2 cache including a store queue having a plurality of entries to store a plurality of information packets; transmitting a request from the L2 cache to the LSU to transfer the information packet to the L2 cache when the L2 cache determines that an available entry exists in the L2 cache store queue; transmitting an acknowledgement from the LSU to the L2 cache, and transferring the information packet from an entry in the LSU store queue to the L2 cache; receiving the information packet in the L2 cache and storing the information packet in the available entry in the L2 cache store queue; and transmitting an additional acknowledgement from the LSU to the L2 cache, in anticipation that the L2 cache has an additional available entry in the L2 cache store queue, and transferring an additional information packet from an additional entry in the LSU store queue to the L2 cache, before the L2 cache requests the additional information packet.

9 . The method of claim 8 , further comprising:
determining by the L2 cache that an additional available entry exists in the L2 cache store queue; storing the additional information packet from the LSU store queue in the additional available entry within the L2 cache store queue; and delaying the transmission of a subsequent request to the LSU for a subsequent information packet to be transferred from the LSU, the subsequent request also serving as an acknowledgement to the LSU for storing the additional information packet in the L2 cache.

10 . The method of claim 8 , wherein the L2 cache includes a control module, and the transmitting of the request by the L2 cache further includes the L2 cache control module transmitting a POP signal along a control bus coupled to the LSU; and
wherein the LSU includes a control module, and the transmitting of the acknowledgement by the LSU further includes the LSU control module transmitting a PUSH signal the control bus coupled to the L2 cache.

11 . The method of claim 10 , wherein the delaying of the request for a subsequent information packet (subsequent request delay) is determined by the L2 cache control module, the L2 cache control module calculating the subsequent request delay based on the number of available entries within the L2 cache store queue.

12 . The method of claim 11 , wherein the L2 cache control module calculates the subsequent request delay based on an average time to transfer the information packet from the LSU store queue to the L2 cache store queue.

13 . The method of claim 11 , wherein the L2 cache control module sets and resets the subsequent request delay based on a threshold, wherein the threshold is the number of available entries in the L2 cache store queue;
wherein the L2 control module sets the subsequent request delay to a fixed time interval when the number of available entries in the L2 cache store queue is less than the threshold; and wherein the L2 cache control module resets the

Assignees

• IBM

Inventors

• Kapoor Shakti
• Wu Nelson
• Dusanapudi Manoj

Classifications

• G06F12/0875 Primary

  with dedicated cache, e.g. instruction or stack · CPC title

• G06F2212/60

  Details of cache memory · CPC title

• G06F12/0897 Primary

  with two or more cache hierarchy levels (with multilevel cache hierarchies G06F12/0811) · CPC title

• G06F9/3834

  Maintaining memory consistency · CPC title