Replicating test case data into a cache with non-naturally aligned data boundaries

US10489259B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-10489259-B2
Application numberUS-201815887968-A
CountryUS
Kind codeB2
Filing dateFeb 2, 2018
Priority dateJan 29, 2016
Publication dateNov 26, 2019
Grant dateNov 26, 2019

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

Data is replicated into a memory cache with non-naturally aligned data boundaries to reduce the time needed to generate test cases for testing a processor. Placing data in the non-naturally aligned data boundaries as described herein allows replicated testing of the memory cache while preserving double word and quad word boundaries in segments of the replicated test data. This allows test cases to be generated for a section of memory and then replicated throughout the memory and tested by a single test branching back and using the next strand of the replicated test data in the memory cache.

First claim

Opening claim text (preview).

The invention claimed is: 1. A computer-implemented method executed by at least one processor for testing a computer processor device comprising: providing test data comprising a plurality of segments of test data that when placed consecutively in a memory together make a slice of test data, wherein each of the plurality of segments making up the slice of test data fill a portion of the memory comprising a plurality of cache lines of the memory; wherein the plurality of test segments are non-naturally aligned where the beginning and ending of each of the plurality of segments when placed consecutively in a memory do not line up with a cache line boundary, wherein the plurality of segments comprise an odd number of words where the odd number is chosen from 5, 7, 9, and 11; placing multiple instances of the slice of test data in consecutive locations in a cache memory; and running a test code on the consecutive slices of test data with non-naturally aligned boundaries by branching back to rerun the test code on each of the slices of test data. 2. The method of claim 1 wherein the step of running a test code on the consecutive slices of test data with non-naturally aligned boundaries further comprises: executing test code with one or more test cases on a first slice of test data of the plurality of test data slices using a base offset; determining if there are additional slices of test data; and where there are additional slices of test data, modifying the base offset to point to a next test data slice and branching back to execute the test code with the modified base offset. 3. The method of claim 1 wherein the plurality of segments of test data comprises sub-segments of test data that include word, double word and quad word sub-segments. 4. The method of claim 3 wherein sub-segments in subsequent segments of the test data are arranged in different orders. 5. The method of claim 1 wherein each segment includes one single word, one double word and one quad word sub-segment. 6. The method of claim 1 wherein the slice of test data further comprises a plurality of strands of test cases that each comprise a plurality of segments. 7. The method of claim 6 wherein the plurality of strands comprises five strands with four segments in each strand with each segment having seven words of test data with four bytes in each word. 8. The apparatus of claim 1 wherein the plurality of segments are non-naturally aligned where the beginning and ending of each of the segments does not line up with a page crossing boundary. 9. The apparatus of claim 1 wherein the plurality of segments are non-naturally aligned where the beginning and ending of each of the segments does not line up with a 32 byte boundary. 10. A computer-implemented method executed by at least one processor for testing a computer processor device comprising: providing test data comprising a plurality of segments of test data that when placed consecutively in a memory together make a slice of test data, wherein each of the plurality of segments making up the slice of test data fill a portion of the memory comprising a plurality of cache lines of the memory; wherein the plurality of test segments are non-naturally aligned where the beginning and ending of each of the plurality of segments when placed consecutively in a memory do not line up with a cache line boundary, wherein the plurality of segments comprise one single word, one double word and one quad word sub-segment, wherein sub-segments in subsequent segments of the test data are arranged in different orders; placing multiple instances of the slice of test data in consecutive locations in a cache memory; and running a test code on the consecutive slices of test data with non-naturally aligned boundaries by branching back to rerun the test code on each of the slices of test data.

Assignees

Inventors

Classifications

  • G06F11/263Primary

    Generation of test inputs, e.g. test vectors, patterns or sequences {; with adaptation of the tested hardware for testability with external testers} · CPC title

  • Data generation devices, e.g. data inverters · CPC title

  • using a storage for the test inputs, e.g. test ROM, script files · CPC title

  • Replication mechanisms · CPC title

  • Multiuser, multiprocessor or multiprocessing cache systems · CPC title

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Frequently asked questions

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What does patent US10489259B2 cover?
Data is replicated into a memory cache with non-naturally aligned data boundaries to reduce the time needed to generate test cases for testing a processor. Placing data in the non-naturally aligned data boundaries as described herein allows replicated testing of the memory cache while preserving double word and quad word boundaries in segments of the replicated test data. This allows test cases…
Who is the assignee on this patent?
IBM
What technology area does this patent fall under?
Primary CPC classification G06F11/263. Mapped technology areas include Physics.
When was this patent published?
Publication date Tue Nov 26 2019 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 12 related publications on this page (citations in our corpus or others sharing the same primary CPC).