Performance and reliability of processor store operation data transfers

Patent metadata

Field	Value
Publication number	US-12141071-B2
Application number	US-202217869956-A
Country	US
Kind code	B2
Filing date	Jul 21, 2022
Priority date	Jul 21, 2022
Publication date	Nov 12, 2024
Grant date	Nov 12, 2024

Abstract

Provided is a processor that includes a load and store unit (LSU) and a cache memory, and transfers data information from a store queue in the LSU to the cache memory. The cache memory requests an information packet from the LSU when the cache memory determines that an available entry exists in a store queue within the cache memory. The LSU acknowledges the request and transfers an information packet to the cache memory. The LSU anticipates that an additional available entry exists in the cache memory, transmits an additional acknowledgement to the cache memory, and transfers an additional information packet, before receiving an additional request from the cache memory.

First claim

What is claimed:

1. A processor included within a central processing unit (CPU), the CPU included within a computer processor system, the CPU coupled to a memory, the processor comprising:
a load and store unit (LSU) including an LSU control module and an LSU store queue, the LSU store queue including a first plurality of entries for storing a first plurality of information packets;
a cache memory (L2 cache) coupled to the LSU, the L2 cache including an L2 cache control module and an L2 cache store queue, the L2 cache store queue including a second plurality of entries for storing a second plurality of information packets;
wherein the L2 cache determines that a free entry of the second plurality of entries exists in the L2 cache store queue, and transmits a request to the LSU to transfer an information packet of the first plurality of information packets based on the determination that the free entry exists in the L2 cache;
wherein the LSU transmits, based on the request, an acknowledgement to the L2 cache and transfers the information packet from an entry of the first plurality of entries in the LSU store queue over a data bus coupled to the L2 cache;
wherein the acknowledgement is different from the information packet;
wherein the L2 cache receives the information packet from the LSU store queue and stores the information packet in the free entry in the L2 cache store queue; and
wherein, before the L2 cache requests an additional information packet from the first plurality of information packets, the LSU anticipates that the L2 cache store queue has an additional free entry in the second plurality of entries, transmits an additional acknowledgement to the L2 cache, and transfers the additional information packet from an additional entry in the first plurality of entries in the LSU store queue.

2. The processor of claim 1 , wherein the L2 cache determines that the additional free entry exists in the L2 cache store queue, receives the additional information packet from the LSU store queue, and stores the additional information packet in the additional free entry within the L2 cache store queue; and
wherein the L2 cache delays transmitting a subsequent request to the LSU for a subsequent information packet of the first plurality of information packets to be transferred from the LSU, the subsequent request also serving as an acknowledgement to the LSU for storing the additional information packet in the L2 cache.

3. The processor of claim 1 , wherein the L2 cache requests the information packet by transmitting a POP signal from the L2 cache control module along a control bus coupled to the LSU control module, and wherein the LSU acknowledges the request from the L2 cache by transmitting a PUSH signal from the LSU control module along the control bus coupled to the L2 cache control module.

4. The processor of claim 2 , wherein the L2 cache control module determines the delay to transmit the subsequent request for the subsequent information packet, and calculates the delay based on a number of free entries in the second plurality of entries within the L2 cache store queue.

5. The processor of claim 4 , wherein the L2 cache control module further calculates the delay based on an average time to transfer the information packet from the LSU store queue to the L2 cache store queue.

6. The processor of claim 4 , wherein the L2 cache control module sets and resets the delay based on a threshold, wherein the threshold is the number of free entries in the L2 cache store queue;
wherein the L2 cache control module sets the delay to a fixed time interval when the number of free entries in the L2 cache store queue is less than the threshold; and
wherein the L2 cache control module resets the delay to no time delay when the number of free entries in the L2 cache store queue is greater than or equal to the threshold.

7. The processor of claim 1 , wherein the L2 cache determines that the additional free entry does not exist in the L2 cache store queue;
wherein the L2 cache control module transmits a BOUNCE signal along a control bus to the LSU control module to indicate that the additional information packet was rejected and not stored in the L2 cache store queue; and
wherein the LSU must wait for a subsequent request from the L2 cache before retrying the transfer of the additional information packet.

8. A method for improving performance of store operation data information transfers within a computer processing system, the computer processing system including a processor and a memory, the processor including a cache memory and a load and store unit, the method comprising:
storing an information packet within the load and store unit (LSU), the information packet to be transferred to the cache memory (L2 cache), the LSU including an LSU store queue having a first plurality of entries to store a first plurality of information packets, the first plurality of information packets includes the information packet, the L2 cache including an L2 cache store queue having a second plurality of entries to store a second plurality of information packets;
determining, by the L2 cache, that a free entry of the second plurality of entries exists in the L2 cache store queue;
transmitting, based on the determination, a request from the L2 cache to the LSU to transfer the information packet to the L2 cache;
transmitting, based on the request, an acknowledgement from the LSU to the L2 cache, and transferring the information packet from an entry of the first plurality of entries in the LSU store queue to the L2 cache, wherein the acknowledgement is different from the information packet;
receiving the information packet in the L2 cache and storing the information packet in the free entry in the L2 cache store queue; and
before the L2 cache requests an additional information packet from the first plurality of information packets, transmitting an additional acknowledgement from the LSU to the L2 cache, in anticipation that the L2 cache has an additional free entry in the second plurality of entries in the L2 cache store queue, and transferring the additional information packet from an additional entry in the first plurality of entries in the LSU store queue to the L2 cache.

9. The method of claim 8 , further comprising:
determining, by the L2 cache, that the additional free entry exists in the L2 cache store queue;
storing the additional information packet from the LSU store queue in the additional free entry within the L2 cache store queue; and
delaying transmission of a subsequent request to the LSU for a subsequent information packet of the first plurality of information packets to be transferred from the LSU, the subsequent request also serving as an acknowledgement to the LSU for storing the additional information packet in the L2 cache.

10. The method of claim 9 , wherein the L2 cache includes an L2 cache control module, and the transmitting of the request by the L2 cache further includes the L2 cache control module transmitting a POP signal along a control bus coupled to the LSU; and
wherein the LSU includes an LSU control module, and the transmitting of the acknowledgement by the LSU further includes the LSU control module transmitting a PUSH signal along the control bus coupled to the L2 cache.

11. The method of claim 10 , wherein the delaying of the transmission of the subsequent request is determined by the L2 cache control module, and the L2 cache control module calculating the delaying of the transmission of the subsequent request based on a number of free entries in the second plurality of entries within the L2 cache store queue.

12. The method of claim 11 , wherein the L2 cache control m

Assignees

• IBM
• Int Business Machnes Corporation

Inventors

• Kapoor Shakti
• Wu Nelson
• Dusanapudi Manoj

Classifications

• G06F2212/60

  Details of cache memory · CPC title

• G06F9/3834

  Maintaining memory consistency · CPC title

• G06F12/0875 Primary

  with dedicated cache, e.g. instruction or stack · CPC title

• G06F12/0897 Primary

  with two or more cache hierarchy levels (with multilevel cache hierarchies G06F12/0811) · CPC title