Phase interpolator (PI) including weighted summing circuit and related methods
US-12592687-B2 · Mar 31, 2026 · US
This page is not indexed by search engines while we improve data quality.
Chen Minhan patents
Chen Minhan is listed as an inventor on 36 patents in our database. Major assignees and classification codes are summarized below.
| Metric | Value |
|---|---|
| Inventor | Chen Minhan |
| Total patents | 36 |
| First publication | Jan 15, 2015 |
| Latest publication | Mar 31, 2026 |
Notable patents
Publications ranked by popularity score, then publication date.
Digital phase-locked loops (PLL) including closed-loop time-to-digital converter (TDC) gain calibration circuits and related methods
US-12463649-B2 · Nov 4, 2025 · US
Time-to-digital converters (TDC) employing a single-stage delay pair and noise shaping for wide input range and reduced quantization noise in a phase-locked loop (PLL)
US-12379695-B2 · Aug 5, 2025 · US
Phase interpolator (PI) with clamping circuit to limit operation to range having optimal integral non-linearity and related methods
US-12362902-B2 · Jul 15, 2025 · US
Phase interpolator (pi) including weighted summing circuit and related methods
US-2025167776-A1 · May 22, 2025 · US
Phase interpolator (pi) with clamping circuit to limit operation to range having optimal integral non-linearity and related methods
US-2025150253-A1 · May 8, 2025 · US
Time to digital converter (tdc) circuit with self-adaptive time granularity and related methods
US-2025147468-A1 · May 8, 2025 · US
Digital phase-locked loops (pll) including closed-loop time-to-digital converter (tdc) gain calibration circuits and related methods
US-2025141456-A1 · May 1, 2025 · US
Time to digital converter (TDC) circuit with self-adaptive time granularity and related methods
US-12216434-B2 · Feb 4, 2025 · US
Phase-locked loops (PLL), including time-to-digital converter (TDC) gain calibration circuits and related methods
US-12212327-B2 · Jan 28, 2025 · US
Recent patents
Latest publications not already listed above.
Time-to-digital converters (tdc) employing a single-stage delay pair and noise shaping for wide input range and reduced quantization noise in a phase-locked loop (pll)
US-2024361729-A1 · Oct 31, 2024 · US
Phase-locked loops (pll), including time-to-digital converter (tdc) gain calibration circuits and related methods
US-2024291495-A1 · Aug 29, 2024 · US
Phase-locked loops (pll) including digitally controlled oscillator (dco) gain calibration circuits and related methods
US-2024267052-A1 · Aug 8, 2024 · US
Peak voltage amplitude detectors tolerant to process variation and device mismatch and related methods
US-11953527-B2 · Apr 9, 2024 · US
Peak voltage amplitude detectors tolerant to process variation and device mismatch and related methods
US-2024069074-A1 · Feb 29, 2024 · US
Time to digital converter (tdc) circuit with self-adaptive time granularity and related methods
US-2023384738-A1 · Nov 30, 2023 · US
Calibrating a phase interpolator by amplifying timing differences
US-11159151-B1 · Oct 26, 2021 · US
Low-power, low-latency time-to-digital-converter-based serial link
US-10965442-B2 · Mar 30, 2021 · US
Low-power, low-latency time-to-digital-converter-based serial link
US-2020106597-A1 · Apr 2, 2020 · US
Receiver with cancellation of intrinsic offset from decision feedback equalization to enhance data margin
US-10505705-B1 · Dec 10, 2019 · US
Offset nulling for high-speed sense amplifier
US-10326417-B1 · Jun 18, 2019 · US
Offset nulling for high-speed sense amplifier
US-2019173440-A1 · Jun 6, 2019 · US
Apparatus and method for calibrating a receiver with a decision feedback equalizer (DFE)
US-10079698-B1 · Sep 18, 2018 · US
Offset calibration for low power and high performance receiver
US-9722823-B2 · Aug 1, 2017 · US
Accurate sample latch offset compensation scheme
US-9614502-B2 · Apr 4, 2017 · US
Accurate sample latch offset compensation scheme
US-2017040983-A1 · Feb 9, 2017 · US
Offset calibration for low power and high performance receiver
US-2016294583-A1 · Oct 6, 2016 · US
Dynamically calibrating the offset of a receiver with a decision feedback equalizer (DFE) while performing data transport operations
US-9444657-B2 · Sep 13, 2016 · US
Built-in test structure for a receiver
US-2016216317-A1 · Jul 28, 2016 · US
Offset calibration for low power and high performance receiver
US-9385695-B2 · Jul 5, 2016 · US
Major assignees
Companies most often associated with this inventor's publications.
| Assignee | Patents |
|---|---|
| Microsoft Technology Licensing Llc | 17 |
| Qualcomm Inc | 13 |
| IBM | 6 |
| Globalfoundries Us 2 Llc | 1 |
Top CPC classifications
Most common classification codes across this inventor's patents.
| CPC | Patents |
|---|---|
| G04F10/005 | 11 |
| H04L25/03057 | 10 |
| H03L7/085 | 9 |
| H03L7/099 | 5 |
| H03K5/135 | 5 |