Digital phase-locked loops (pll) including closed-loop time-to-digital converter (tdc) gain calibration circuits and related methods

Patent metadata

Field	Value
Publication number	US-2025141456-A1
Application number	US-202318385729-A
Country	US
Kind code	A1
Filing date	Oct 31, 2023
Priority date	Oct 31, 2023
Publication date	May 1, 2025
Grant date	—

Abstract

In a calibrated digital phase-locked-loop (DPLL) circuit, during a normal operating mode, a control value provided to a digitally controlled oscillator (DCO) is updated by a feedback circuit to keep an output clock generated by the DCO synchronized with a reference clock. The feedback circuit includes a time-to-digital converter (TDC) circuit to measure a phase difference as a time interval. In a calibration operating mode of the calibrated DPLL circuit, calibration of a resolution of a time measurement of the time interval measured by the TDC is performed in the feedback circuit while the control value provided to the DCO is kept constant. Calibrating the TDCs in each of the DPLLs in an integrated circuit (IC) to a nominal resolution in this manner improves synchronization of the clock domains. In some examples, the TDC circuit is a Vernier type circuit and calibration sets a delay difference to a nominal resolution.

First claim

What is claimed is:

1 . A calibrated digital phase-locked loop (DPLL), comprising:
a digitally controlled oscillator (DCO) circuit configured to generate a first output clock having a first frequency based on a control value; and a feedback circuit configured to:
in a normal operating mode:
generate a first measurement of a first time interval corresponding to a phase difference between the first output clock and a reference clock; and
update the control value based on the first measurement; and

in a calibration operating mode:
keep the control value constant; and
adjust a first resolution of the first measurement to be closer to a nominal resolution.

2 . The calibrated DPLL of claim 1 , wherein the feedback circuit is further configured to:
in the normal operating mode, generate the first measurement in a range having a maximum value comprising a first multiple of the first resolution; and in the calibration operating mode:
generate a second measurement of a second time interval greater than the first time interval, wherein the second measurement comprises a second multiple of the first resolution and the second multiple is greater than the first multiple; and
compare the second measurement to a third measurement of the second time interval, the third measurement comprising a third multiple of the nominal resolution.

3 . The calibrated DPLL of claim 1 , wherein the second multiple is at least two times the first multiple.

4 . The calibrated DPLL of claim 2 , wherein:
the feedback circuit further comprises:
a first clock divider configured to divide the first output clock to generate a feedback clock having a second frequency lower than the first frequency;
a phase frequency detector (PFD) comprising:
a first PFD input configured to receive a reference signal; and
a second PFD input configured to receive a feedback signal;
wherein the PFD is configured to generate a start signal and a stop signal separated by an amount of time based on a phase difference between the reference signal and the feedback signal; and

a time-to-digital converter (TDC) circuit comprising:
serially coupled first delay circuits each having a first propagation delay and configured to propagate the start signal;
serially coupled second delay circuits each having a second propagation delay, shorter than the first delay, and configured to propagate the stop signal; and
a TDC output configured to generate a time measurement of an amount of time separating the start signal and the stop signal as the control value;
wherein:
in the normal operating mode:
 the reference signal comprises the reference clock;
 the feedback signal comprises the feedback clock; and
 the time measurement comprises the first measurement;
a first resolution of the time measurement comprises a difference between the first propagation delay and the second propagation delay; and
the first multiple corresponds to a number of first delay circuits in the serially coupled first delay circuits.

5 . The calibrated DPLL of claim 4 , wherein the feedback circuit further comprises a delay feedback circuit configured to, in the calibration operating mode:
feedback an output of the serially coupled first delay circuits to an input of the serially coupled first delay circuits; and feedback an output of the serially coupled second delay circuits to an input of the serially coupled second delay circuits.

6 . The calibrated DPLL of claim 5 , wherein the feedback circuit further comprises a lap counter configured to increment each time the output of the serially coupled second delay circuits is fed back to the input of the serially coupled second delay circuits.

7 . The calibrated DPLL of claim 4 , wherein:
the feedback circuit further comprises a value register configured to store the control value; and the value register is configured to:
in the normal operating mode, update the control value based on the time measurement and store the updated control value; and
in the calibration operating mode, feedback a stored control value to keep the control value constant.

8 . The calibrated DPLL of claim 4 , further comprising a resolution adjustor circuit configured to, in the calibration operating mode:
store the time measurement generated on the TDC output; compare the time measurement having the first resolution to a predetermined time measurement of the time separating the start signal and the stop signal having the nominal resolution; and generate a resolution adjustment signal to adjust the first resolution.

9 . The calibrated DPLL of claim 8 , wherein the resolution adjustment signal is configured to update at least one of the first propagation delay and the second propagation delay.

10 . The calibrated DPLL of claim 8 , further comprising a calibration mode indication circuit configured to periodically generate a calibration mode indicator indicating the calibration mode in response to a calibration enable signal.

11 . The calibrated DPLL of claim 10 , wherein the resolution adjustor circuit is configured to accumulate results of comparing the time measurement and the predetermined time measurement in respective instances of the calibration mode to generate the resolution adjustment signal.

12 . The calibrated DPLL of claim 4 , further comprising a calibration interval generator circuit configured to, in the calibration mode, provide a calibration reference signal on the first PFD input and a calibration feedback signal on the second PFD input, wherein the calibration reference signal and the calibration feedback signal are separated in time by the second time interval.

13 . The calibrated DPLL of claim 12 , further comprising a second clock divider configured to divide the first output clock to generate a test clock having a test clock period, wherein the second time interval is based on the test clock period.

14 . A method of operating a calibrated digital phase-locked loop (DPLL), comprising:
generating, in a digitally controlled oscillator (DCO) circuit, a first output clock having a first frequency based on a control value; and in a feedback circuit:
in a normal operating mode:
generating a first measurement of a first time interval corresponding to a phase difference between the first output clock and a reference clock; and
updating the control value based on the first measurement; and

in a calibration operating mode:
keeping the control value constant; and
adjusting a first resolution of the first measurement to be closer to a nominal resolution.

15 . The method of claim 14 , further comprising:
in the normal operating mode, generating the first measurement in a range having a maximum value comprising a first multiple of the first resolution; and in the calibration operating mode:
generating a second measurement of a second time interval greater than the first time interval, wherein the second measurement comprises a second multiple of the first resolution and the second multiple is greater than the first multiple; and
comparing the second measurement to a third measurement of the second time interval, the third measurement comprising a third multiple of the nominal resolution.

16 . The method of claim 15 , further comprising:
dividing the first output clock to generate a feedback clock having a second frequency lower than the first frequency; generating, in a phase frequency detector, a start signal and a stop signal separated by an amount of time based on a phase difference between a reference signal and a feedback signal; and generating

Assignees

• Microsoft Technology Licensing Llc

Inventors

• Lu Ping
• Chen Minhan
• Desai Shaishav A

Classifications

• H03L7/0991

  the oscillator being a digital oscillator, e.g. composed of a fixed oscillator followed by a variable frequency divider (H03L7/0995 takes precedence; fixed oscillators with means for selecting among various phases H03L7/0814) · CPC title

• H03L7/085 Primary

  concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal (H03L7/10 takes precedence; circuits for comparing the phase or frequency of two mutually-independent oscillations H03D13/00) · CPC title

• G04F10/005

  Time-to-digital converters [TDC] (analog-to-digital converters with intermediate conversion to time or phase H03M1/50, H03M1/60) · CPC title

• H03L7/07

  using several loops, e.g. for redundant clock signal generation · CPC title

• H03L7/1075 Primary

  by changing characteristics of the loop filter, e.g. changing the gain, changing the bandwidth (H03L7/1072 takes precedence) · CPC title