Offset calibration for low power and high performance receiver

Patent metadata

Field	Value
Publication number	US-9385695-B2
Application number	US-201414298718-A
Country	US
Kind code	B2
Filing date	Jun 6, 2014
Priority date	Jun 6, 2014
Publication date	Jul 5, 2016
Grant date	Jul 5, 2016

Abstract

Systems and methods for providing offset calibration for low power and high performance receivers are described herein. In one embodiment, a method for offset calibration comprises inputting a first voltage to a first input of a sample latch, and inputting a second voltage and an offset-cancellation voltage to a second input of the sample latch. The method also comprises adjusting the offset-cancellation voltage, observing an output of the sample latch as the offset-cancellation voltage is adjusted, and recording a value of the offset-cancellation voltage at which a metastable state is observed at the output of the sample latch. The method may be performed for each one of a plurality of different voltage levels for the first voltage to determine an offset-cancellation voltage for each one of the voltage levels.

First claim

What is claimed is:

1. A receiver, comprising:
a summing amplifier having an input configured to receive a data signal, and an output;
a first sample latch having a first input coupled to the output of the summing amplifier, and a second input;
a first digital-to-analog converter (DAC) having an output coupled to the second input of the first sample latch, wherein the first DAC is configured to receive a first offset code, to convert the first offset code into a first offset-cancellation voltage, and to output the first offset-cancellation voltage to the second input of the first sample latch;
a second sample latch having a first input coupled to the output of the summing amplifier, and a second input; and
a second DAC having an output coupled to the second input of the second sample latch, wherein the second DAC is configured to receive a second offset code, to convert the second offset code into a second offset-cancellation voltage, and to output the second offset-cancellation voltage to the second input of the second sample latch.

2. The receiver of claim 1 , further comprising a processor configured to determine a target voltage level for the data signal at the first input of the second sample latch, and to select the second offset code from a plurality of offset codes corresponding to different voltage levels based on the determined target voltage level.

3. The receiver of claim 1 , wherein the second DAC is further configured to receive a code corresponding to a threshold voltage, to convert the received code into the threshold voltage, and to output the threshold voltage to the second input of the second sample latch, wherein the threshold voltage corresponds to a target voltage level for the data signal.

4. The receiver of claim 3 , wherein the threshold voltage has approximately the same magnitude as the target voltage level.

5. The receiver of claim 4 , wherein the threshold voltage has a magnitude of at least 50 mV.

6. The receiver of claim 3 , further comprising a processor configured to observe an output of the second sample latch, and to adjust a parameter of the receiver until a metastable state is observed at the output of the second sample latch.

7. The receiver of claim 5 , wherein the processor is configured to adjust a parameter of the receiver by adjusting at least one of a parameter of an equalizer in the receiver and a gain of an amplifier in the receiver.

8. The receiver of claim 1 , further comprising:
a decision feedback equalizer (DFE) coupled to an output of the first sample latch, wherein the DFE is configured to compute an inter symbol interference (ISI)-cancellation value based on one or more bits from the output of the first sample latch, and to output an ISI-cancellation code corresponding to the ISI-cancellation value; and
a third DAC configured to convert the ISI-cancellation code into a ISI-cancellation voltage, and to output the ISI-cancellation voltage to the summing amplifier, wherein the summing amplifier applies the ISI-cancellation voltage to the data signal to remove ISI corresponding to the one or more bits.

9. A receiver, comprising:
a sample latch having a first input coupled to a receive data path, and a second input;
a first digital-to-analog converter (DAC) having an output coupled to the second input of the sample latch;
a second DAC having an output;
a switch configured to selectively couple the output of the second DAC to the first input of the sample latch; and
a calibration controller, wherein, in a data mode, the calibration controller is configured to open the switch, and, in a calibration mode, the calibration controller is configured to close the switch to couple the output of the second DAC to the first input of the sample latch;
wherein, in the data mode, the first input of the sample latch receives a data signal from the receive data path, and, in the calibration mode, the calibration controller inputs a code to the second DAC, the second DAC converts the received code into a calibration voltage, and outputs the calibration voltage to the first input of the sample latch to calibrate an offset of the sample latch at the calibration voltage.

10. The receiver of claim 9 , wherein the calibration voltage has a magnitude of at least 50 mV.

11. The receiver of claim 9 , wherein, in the calibration mode, the calibration controller is configured to adjust an offset-cancellation voltage output by the first DAC to the second input of the sample latch by inputting a plurality of different offset codes to the first DAC, to observe an output of the sample latch as the offset-cancellation voltage is adjusted, and to record an offset code from the plurality of offset codes at which a metastable state is observed at the output of the sample latch.

12. The receiver of claim 11 , further comprising a processor configured to, in the data mode, input the recorded offset code to the first DAC if a target voltage level for the data signal corresponds to the calibration voltage.

13. The receiver of claim 9 , further comprising a processor configured to, in the data mode, input a threshold code to the first DAC corresponding to a threshold voltage, wherein the first DAC converts the threshold code into the threshold voltage, and outputs the threshold code to the second input of the sample latch, wherein the threshold voltage corresponds to a target voltage level for the data signal.

14. The receiver of claim 13 , wherein, in the data mode, the processor is configured to observe an output of the sample latch, and to adjust a parameter of the receiver until a metastable state is observed at the output of the sample latch.

15. The receiver of claim 14 , wherein, in the data mode, the processor is configured to adjust the parameter of the receiver by adjusting at least one of a parameter of an equalizer in the receiver and a gain of an amplifier in the receiver.

16. The receiver of claim 9 , further comprising an amplifier configured to amplify the data signal and to output the amplified data signal to the first input of the sample latch, wherein the calibration controller is configured to disable the amplifier in the calibration mode.

Assignees

• Qualcomm Inc

Inventors

• Chen Minhan
• Arcudia Kenneth Luis

Classifications

• H04L25/061 Primary

  providing hard decisions only; arrangements for tracking or suppressing unwanted low frequency components, e.g. removal of DC offset (removal of DC offset in coupling arrangements H04L25/029, H04L25/0296) · CPC title

• H03K5/003 Primary

  Changing the DC level (reinsertion of DC component of a television signal H04N5/16) · CPC title

• H04L25/0296

  Arrangements to ensure DC-balance · CPC title

• H04L25/03057

  with a recursive structure (H04L25/03031 takes precedence) · CPC title

• H04L25/0272

  Arrangements for coupling to multiple lines, e.g. for differential transmission · CPC title