Receiver with cancellation of intrinsic offset from decision feedback equalization to enhance data margin

Patent metadata

Field	Value
Publication number	US-10505705-B1
Application number	US-201816233647-A
Country	US
Kind code	B1
Filing date	Dec 27, 2018
Priority date	Dec 27, 2018
Publication date	Dec 10, 2019
Grant date	Dec 10, 2019

Abstract

A receiver is provided that generates a data sampling clock that is offset by clock offset that is a function of a decision feedback equalizer gain to account for a data sampling timing error that would occur without the clock delay.

First claim

We claim:

1. A receiver, comprising:
a finite impulse response filter configured to generate a feedback signal responsive to a gain for a decision feedback equalizer;
an adder configured to subtract the feedback signal from a pre-adder received data signal to form a post-adder received data signal; and
a clock data recovery circuit configured to generate a data sampling clock signal that is advanced in phase with respect to data transitions in the post-adder received data signal by a clock offset responsive to the gain for the decision feedback equalizer.

2. The receiver of claim 1 , further comprising:
a slicer configured to sample the post-adder received data signal responsive to the data sampling clock signal to form a series of data samples.

3. The receiver of claim 2 , wherein the slicer comprises an in-phase slicer, the receiver further comprising a quadrature-phase slicer configured to sample the post-adder received data signal to form a series of quadrature data samples.

4. The receiver of claim 3 , further comprising a phase detector configured to determine a phase between the series of data samples and the series of quadrature data samples.

5. The receiver of claim 1 , further comprising:
a linear equalizer configured to equalize a received data signal to form the pre-adder received data signal.

6. The receiver of claim 1 , further comprising a logic circuit configured to map the gain for the decision feedback equalizer into the clock offset.

7. The receiver of claim 2 , wherein the slicer is further configured to sample the post-adder received data signal responsive to a complement of the data sampling clock signal.

8. The receiver of claim 1 , wherein the clock data recovery circuit is further configured to generate an edge-locked clock signal that is locked to data transitions in the post-adder received data signal, and wherein the clock data recovery circuit is further configured to generate the data sampling clock signal to be advanced in phase by the clock offset with respect to a quadrature of the edge-locked clock signal.

9. The receiver of claim 1 , wherein the clock data recovery circuit is further configured to generate an offset edge-locked clock signal that is offset with respect to data transitions in the post-adder received data signal by the clock offset, and wherein the clock data recovery circuit is further configured to generate the data sampling clock signal to be in quadrature with the offset edge-locked clock signal.

10. A method for a receiver, comprising:
generating a feedback signal responsive to a gain for a decision feedback equalizer;
subtracting the feedback signal from a pre-adder received data signal to form a post-adder received data signal;
mapping the gain for the decision feedback equalizer into a clock offset;
generating a data sampling clock signal that is advance in phase with respect to the post-adder received data signal by the clock offset; and
sampling the post-adder received data signal responsive to the data sampling clock signal to form a series of data samples.

11. The method of claim 10 , further comprising:
generating the mapping by an empirical test of an integrated circuit including the receiver.

12. The method of claim 10 , further comprising:
generating the mapping using a simulation of the receiver.

13. The method of claim 10 , further comprising:
generating an edge-locked clock signal that is locked to data transitions in the post-adder received data signal, wherein the data sampling clock signal is offset by the clock offset with respect to a quadrature with the edge-locked clock signal.

14. The method of claim 10 , further comprising:
linearly equalizing a received data signal to form the pre-adder received data signal.

15. The method of claim 10 , wherein the subtracting of the feedback signal from the pre-adder received data signal to form the post-adder received data signal delays the post-adder received data signal by an adder delay that varies according to the gain for the decision feedback equalizer.

16. The method of claim 15 , wherein the clock offset substantially equals the adder delay.

17. A receiver, comprising:
a decision feedback equalizer including a digital control logic circuit configured to generate a decision feedback equalizer gain for a feedback signal;
an adder configured to subtract the feedback signal from a pre-adder received data signal to form a post-adder received data signal;
an in-phase slicer configured to sample the post-adder received data signal responsive to an adjusted in-phase clock signal to generate in-phase data samples;
a quadrature-phase slicer configured to sample the post-adder received data signal responsive to a quadrature clock signal to generate quadrature data samples;
means for mapping the decision feedback equalizer gain into a clock offset that substantially equals an un-cancelled inter-symbol interference for the quadrature data samples; and
a clock data recovery circuit configured to generate the adjusted in-phase clock signal that is advanced in phase with respect to data transitions in the post-adder received data signal by the clock offset.

18. The receiver of claim 17 , wherein the clock data recovery circuit is further configured to generate the quadrature clock signal to be advanced in phase with respect to the data transitions in the post-adder received data signal by the clock offset, and wherein the adjusted in-phase clock signal is in quadrature with the quadrature clock signal.

19. The receiver of claim 18 , wherein the clock data recovery circuit is further configured to generate the adjusted in-phase clock signal to be advanced in phase by the clock offset with respect to being in quadrature to the quadrature clock signal.

20. The receiver of claim 17 , further comprising a phase detector configured to determine a phase between the in-phase data samples and the quadrature data samples.

Assignees

• Qualcomm Inc

Inventors

• Chen Minhan
• Sun Li
• Chang Chia Heng
• Goudarzi Hadi
• Deans Russell

Classifications

• H04L7/0337

  Selecting between two or more discretely delayed clocks or selecting between two or more discretely delayed received code signals · CPC title

• H04L7/0025 Primary

  interpolation of clock signal · CPC title

• H04L25/03885

  adaptive · CPC title

• H04L25/03038 Primary

  with a non-recursive structure (H04L25/03031 takes precedence) · CPC title

• H04L25/03267

  with decision feedback equalisers · CPC title