Phase interpolator (PI) with clamping circuit to limit operation to range having optimal integral non-linearity and related methods

Patent metadata

Field	Value
Publication number	US-12362902-B2
Application number	US-202318386980-A
Country	US
Kind code	B2
Filing date	Nov 3, 2023
Priority date	Nov 3, 2023
Publication date	Jul 15, 2025
Grant date	Jul 15, 2025

Abstract

A phase-interpolator (PI) circuit generates an interpolated clock to capture data in a capture circuit at a target phase in a phase range between two reference clocks based on an interpolation code within a range of interpolation codes is described. A clamping circuit coupled to the PI circuit provides an interpolation code within a reduced range, where the integral non-linearity (INL) of the interpolated clocks is below a threshold, such that data capture based on the interpolated clock has a lower bit error rate (BER). As a result, the interpolated clock is generated within a reduced phase range corresponding to the reduced range of interpolation codes. When a target phase for an interpolated clock is outside the reduced phase range, the clamping circuit may adjust the target phase clock relative to a reference clock to adjust the target phase to be within the reduced phase range for improved BER.

First claim

What is claimed is:

1. A clamped phase interpolator, comprising:
a phase interpolator configured to generate an interpolator clock having a first phase in a first phase range based on a first interpolation code in a first range of interpolation codes; and
a clamping circuit configured to:
receive an indication of a reduced range of interpolation codes comprising less than all of the first range of interpolation codes, wherein the reduced range of interpolation codes corresponds to a reduced phase range comprising a portion of the first phase range;
receive a target phase clock having a target phase; and
provide, to the phase interpolator, the first interpolation code corresponding to the target phase in the reduced range of interpolation codes.

2. The clamped phase interpolator of claim 1 , further configured to adjust the target phase clock relative to a first reference clock to adjust the target phase to be within the reduced phase range.

3. The clamped phase interpolator of claim 2 , wherein the clamping circuit is further configured to adjust the target phase of the target phase clock based on a phase difference between the target phase and the interpolator phase.

4. The clamped phase interpolator of claim 2 , wherein the reduced phase range is between a first reference phase of the first reference clock and a second reference phase of a second reference clock.

5. The clamped phase interpolator of claim 1 , wherein a first portion of the reduced phase range is between a first reference phase of a first reference clock and a second reference phase of a second reference clock and a second portion of the reduced phase range is not between the first reference phase of the first reference clock and the second reference phase of the second reference clock.

6. The clamped phase interpolator of claim 2 , wherein the clamping circuit is further configured to adjust a delay of a delay circuit configured to provide the target phase clock.

7. The clamped phase interpolator of claim 2 , wherein the clamping circuit is further configured to adjust a delay of delay circuits configured to provide the first reference clock.

8. The clamped phase interpolator of claim 1 , wherein the clamping circuit is further configured to adjust the first interpolation code based on a phase difference between the target phase and the interpolator phase.

9. The clamped phase interpolator of claim 2 , wherein the clamping circuit is further configured to select, based on the target phase, the first reference clock from among a plurality of reference clocks at a first frequency.

10. The clamped phase interpolator of claim 1 , wherein:
the first phase range extends from a minimum interpolation code to a first maximum interpolation code;
the indication of the reduced range of interpolation codes comprises a second maximum interpolation code less than the first maximum interpolation code; and
the reduced range of interpolation codes extends from the minimum interpolation code to the second maximum interpolation code.

11. The clamped phase interpolator of claim 10 , the phase interpolator comprising:
a first phase interpolation circuit configured to generate a first interpolated clock having a second phase between a first reference phase of a first reference clock and a second reference phase of a second reference clock, wherein the first phase is based on the first interpolation code;
a second phase interpolation circuit configured to generate a second interpolated clock having a third phase between a third reference phase of a third reference clock and a fourth reference phase of a fourth reference clock based on a second interpolation code comprising a sum of the first interpolation code and a code offset; and
a summing circuit configured to generate the interpolator clock having the first phase between the second phase of the first interpolated clock and the third phase of the second interpolated clock.

12. The clamped phase interpolator of claim 11 , wherein in response to the sum of the first interpolation code and the code offset being less than or equal to the second maximum interpolation code:
the second interpolation code comprises the sum;
the third reference clock comprises the first reference clock; and
the fourth reference clock comprises the second reference clock.

13. The clamped phase interpolator of claim 11 , wherein in response to the sum of the first interpolation code and the code offset being more than the second maximum interpolation code:
the second interpolation code comprises the sum minus the first maximum interpolation code; and
the third reference clock comprises the second reference clock.

14. An integrated circuit (IC) comprising:
a sequential logic circuit configured to store data in response to a system clock;
a capture circuit configured to, in each cycle of the system clock, receive the data from the sequential logic circuit in response to an interpolator clock; and
a clamped phase interpolator, comprising:
a phase interpolator configured to generate the interpolator clock having a first phase in a first phase range based on a first interpolation code in a first range of interpolation codes; and
a clamping circuit configured to:
receive an indication of a reduced range of interpolation codes comprising less than all of the first range of interpolation codes, wherein the reduced range of interpolation codes corresponds to a reduced phase range comprising a portion of the first phase range;
receive a target phase clock having a target phase;
provide, to the phase interpolator, the first interpolation code corresponding to the target phase in the reduced range of interpolation codes.

15. The IC of claim 14 , wherein the clamping circuit is further configured to adjust the target phase of the target phase clock relative to a first reference clock to be within the reduced phase range.

16. The IC of claim 15 , wherein the clamping circuit is further configured to adjust a delay to change a timing of the first reference clock.

17. The IC of claim 14 , wherein the clamping circuit is further configured to adjust the first interpolation code based on a phase difference between the target phase and the interpolator phase.

18. The IC of claim 14 , wherein the clamping circuit is further configured to adjust the target phase of the target phase clock relative to a first reference clock and a second reference clock based on a phase difference between the target phase and the interpolator phase.

19. The IC of claim 15 , wherein the clamping circuit is further configured to select, based on the target phase, the first reference clock from among a plurality of reference clocks.

20. The IC of claim 14 , wherein:
the first range of interpolation codes extends from a minimum interpolation code to a first maximum interpolation code;
the indication of the reduced range of interpolation codes comprises a second maximum interpolation code in the first range of interpolation codes and less than the first maximum interpolation code; and
the reduced range of interpolation codes extends from the minimum interpolation code to the second maximum interpolation code.

21. A method in clamped phase interpolator, comprising:
generating an interpolator clock having an interpolator phase in a first phase range based on a first interpolation code in a first range of interpolation codes;
receiving a target phase clock having a target phase;
receiving an indication of a reduced range of interpol

Assignees

• Microsoft Technology Licensing Llc

Inventors

• Lu Ping
• Chen Minhan

Classifications

• H03K2005/00052

  by mixing the outputs of fixed delayed signals with each other or with the input signal · CPC title

• H04L7/02 Primary

  Speed or phase control by the received code signals, the signals containing no special synchronisation information {(H04L7/0075 takes precedence)} · CPC title

• H03K5/135 Primary

  by the use of time reference signals, e.g. clock signals · CPC title