Calibrating a phase interpolator by amplifying timing differences

Patent metadata

Field	Value
Publication number	US-11159151-B1
Application number	US-202017082273-A
Country	US
Kind code	B1
Filing date	Oct 28, 2020
Priority date	Oct 28, 2020
Publication date	Oct 26, 2021
Grant date	Oct 26, 2021

Abstract

Systems and methods related to calibrating a phase interpolator by amplifying timing differences are described. An example system includes a calibration stage configured to output a calibration code for a phase interpolator. The system further includes control logic configured to: (1) at least partially discharge a first pre-charged capacitive load in response to a signal output by the phase interpolator based on the calibration code, and (2) at least partially discharge a second pre-charged capacitive load in response to a reference signal associated with the phase interpolator. The system further includes a feedback path configured to provide feedback to the calibration stage to allow for a modification of the calibration code, where the feedback is dependent on a first voltage provided by the first pre-charged capacitive load and a second voltage provided by the second pre-charged capacitive load.

First claim

What is claimed:

1. A system comprising:
a calibration stage configured to output a calibration code for a phase interpolator;
control logic configured to: (1) at least partially discharge a first pre-charged capacitive load at least in response to a signal output by the phase interpolator based on the calibration code, and (2) at least partially discharge a second pre-charged capacitive load at least in response to a reference signal associated with the phase interpolator; and
a feedback path configured to provide feedback to the calibration stage to allow for a modification of the calibration code, wherein the feedback is dependent on a first voltage provided by the first pre-charged capacitive load after at least partial discharging of the first pre-charged capacitive load and a second voltage provided by the second pre-charged capacitive load after at least partial discharging of the second pre-charged capacitive load.

2. The system of claim 1 , wherein the first pre-charged capacitive load is substantially equal to the second pre-charged capacitive load, wherein during calibration of one of interpolated phases output by the phase interpolator, the second pre-charged capacitive load is discharged only once and the first pre-charged capacitive load is discharged K number of times, and wherein K is a positive integer greater than one.

3. The system of claim 1 , wherein the second pre-charged capacitive load is K number of times the first pre-charged capacitive load, and wherein K is a positive number greater than one, and wherein during calibration of one of interpolated phases output by the phase interpolator each of the first pre-charged capacitive load and the second pre-charged capacitive load is discharged one or more number of times.

4. The system of claim 1 further comprising a comparator, a first inverter coupled to receive the first voltage, and a second inverter coupled to receive the second voltage, and wherein the feedback is determined by using the comparator comparing at least one rising edge of at least one pulse output by the first inverter with at least one rising edge of at least one pulse output by the second inverter.

5. The system of claim 1 further comprising a voltage comparator, wherein the feedback is determined by comparing a magnitude of the first voltage and a magnitude of the second voltage using the voltage comparator.

6. The system of claim 1 , wherein the reference signal is based on a reference clock source associated with the system.

7. The system of claim 1 , wherein the first pre-charged capacitive load comprises a first capacitive array, wherein the second pre-charged capacitive load comprises a second capacitive array, and wherein each of the first pre-charged capacitive load and the second pre-charged capacitive load is discharged at a constant current.

8. A method for calibrating a phase interpolator, the method comprising:
at least partially discharging a first pre-charged capacitive load at least in response to a signal output by the phase interpolator;
at least partially discharging a second pre-charged capacitive load at least in response to a reference signal associated with the phase interpolator; and
providing feedback to a calibration stage associated with the phase interpolator to modify a signal output by the phase interpolator, wherein the feedback is dependent on a first voltage provided by the first pre-charged capacitive load after at least partial discharging of the first pre-charged capacitive load and a second voltage provided by the second pre-charged capacitive load after at least partial discharging of the second pre-charged capacitive load.

9. The method of claim 8 , wherein the first pre-charged capacitive load is substantially equal to the second pre-charged capacitive load, wherein the method further comprises:
during calibration of one of interpolated phases output by the phase interpolator, at least partially discharging the second pre-charged capacitive load only once and at least partially discharging the first pre-charged capacitive load K number of times, and wherein K is a positive integer greater than one.

10. The method of claim 8 , wherein the second pre-charged capacitive load is K number of times the first pre-charged capacitive load, wherein K is a positive number greater than one, and wherein the method further comprises:
during calibration of one of interpolated phases output by the phase interpolator at least partially discharging each of the first pre-charged capacitive load and the second pre-charged capacitive load one or more number of times.

11. The method of claim 10 , further comprising:
processing the first voltage using a first inverter,
processing the second voltage using a second inverter; and
determining the feedback by comparing at least one rising edge of at least one pulse output by the first inverter with at least one rising edge of at least one pulse output by the second inverter.

12. The method of claim 8 , further comprising determining the feedback by comparing a magnitude of the first voltage with a magnitude of the second voltage.

13. The method of claim 8 , wherein the reference signal is based on a reference clock source associated with a system including the phase interpolator.

14. The method of claim 8 , wherein the first pre-charged capacitive load comprises a first capacitive array, wherein the second pre-charged capacitive load comprises a second capacitive array, and wherein each of the first pre-charged capacitive load and the second pre-charged capacitive load is discharged at a constant current.

15. A system comprising:
a calibration stage configured to output a digital calibration code for a phase interpolator;
control logic configured to: (1) at least partially discharge a first pre-charged capacitive load at least in response to a signal output by the phase interpolator based on the digital calibration code, and (2) at least partially discharge a second pre-charged capacitive load at least in response to a reference signal associated with the phase interpolator, wherein the first pre-charged capacitive load is substantially equal to the second pre-charged capacitive load, wherein during calibration of one of interpolated phases output by the phase interpolator, the second pre-charged capacitive load is discharged only once and the first pre-charged capacitive load is discharged K number of times, and wherein K is a positive integer greater than one; and
a feedback path configured to provide feedback to the calibration stage to allow for a modification of the digital calibration code, wherein the feedback is dependent on a first voltage provided by the first pre-charged capacitive load after at least partial discharging of the first pre-charged capacitive load and a second voltage provided by the second pre-charged capacitive load after at least partial discharging of the second pre-charged capacitive load.

16. The system of claim 15 further comprising a comparator, a first inverter coupled to receive the first voltage, and a second inverter coupled to receive the second voltage, and wherein the feedback is determined by using the comparator comparing at least one rising edge of at least one pulse output by the first inverter with at least one rising edge of at least one pulse output by the second inverter.

17. The system of claim 15 further comprising a voltage comparator, wherein the feedback is determined by comparing a magnitude of the first voltage and a magnitude of the second voltage using the voltage comparator.

18. The system

Assignees

• Microsoft Technology Licensing Llc

Inventors

• Lu Ping
• Chen Minhan

Classifications

• H03L7/0814 Primary

  the phase shifting device being digitally controlled · CPC title

• H03K2005/00286

  Phase shifter, i.e. the delay between the output and input pulse is dependent on the frequency, and such that a phase difference is obtained independent of the frequency · CPC title

• H04L7/0025

  interpolation of clock signal · CPC title

• H03K5/135 Primary

  by the use of time reference signals, e.g. clock signals · CPC title

• H03F3/2175

  using analogue-digital or digital-analogue conversion (H03F3/2173 takes precedence) · CPC title