Offset calibration for low power and high performance receiver

Patent metadata

Field	Value
Publication number	US-9722823-B2
Application number	US-201615175990-A
Country	US
Kind code	B2
Filing date	Jun 7, 2016
Priority date	Jun 6, 2014
Publication date	Aug 1, 2017
Grant date	Aug 1, 2017

Abstract

Systems and methods for providing offset calibration for low power and high performance receivers are described herein. In one embodiment, a receiver comprises a sample latch having a first input coupled to a receive data path, and a second input. The receive also comprises a first digital-to-analog converter (DAC), a second DAC, and a calibration controller. In a calibration mode, the calibration controller is configured to input a calibration voltage to the first input of the sample latch using the first DAC, to input a threshold voltage and an offset-cancelation voltage to the second input of the sample latch using the second DAC, to adjust the offset-cancelation voltage, to observe an output of the sample latch as the offset-cancelation voltage is adjusted, and to store a value of the offset-cancelation voltage at which a metastable state is observed at the output of the sample latch in a memory.

First claim

What is claimed is:

1. A method for offset calibration, comprising:
in a calibration mode, performing the steps of:
inputting a calibration voltage to a first input of a sample latch in a receiver;
inputting a threshold voltage and an offset-cancelation voltage to a second input of the sample latch;
adjusting the offset-cancelation voltage;
observing an output of the sample latch as the offset-cancelation voltage is adjusted; and
storing a value of the offset-cancelation voltage at which a metastable state is observed at the output of the sample latch in a memory; and

in a data mode, performing the steps of:
retrieving the value of the offset-cancelation voltage from the memory;
setting the offset-cancelation voltage according to the retrieved value;
inputting the threshold voltage and the set offset-cancelation voltage to the second input of the sample latch, wherein the set offset-cancelation voltage cancels out an offset voltage at the sample latch; and
inputting a data signal to the first input of the sample latch.

2. The method of claim 1 , wherein the threshold voltage corresponds to a target voltage level for the data signal.

3. The method of claim 2 , wherein, in the data mode, the sample latch is configured to output a bit value of one or zero depending on whether a voltage of the data signal is above or below the target voltage level.

4. The method of claim 1 , wherein the calibration voltage and the threshold voltage have the same magnitude and opposite polarities.

5. The method of claim 1 , wherein the threshold voltage has a magnitude of at least 50 mV.

6. The method of claim 1 , wherein, in the data mode, the method further comprises:
observing the output of the sample latch; and
adjusting a gain of an amplifier until a metastable state is observed at the output of the sample latch, wherein the amplifier amplifies the data signal before the data signal is input the first input of the sample latch.

7. An apparatus for offset calibration, comprising:
means for inputting, in a calibration mode, a calibration voltage to a first input of a sample latch;
means for inputting, in the calibration mode, a threshold voltage and an offset-cancelation voltage to a second input of the sample latch;
means for adjusting, in the calibration mode, the offset-cancelation voltage;
means for observing, in the calibration mode, an output of the sample latch as the offset-cancelation voltage is adjusted;
means for storing a value of the offset-cancelation voltage at which a metastable state is observed at the output of the sample latch;
means for retrieving, in a data mode, the stored value of the offset-cancelation voltage;
means for setting, in the data mode, the offset-cancelation voltage according to the retrieved value;
means for inputting, in the data mode, the threshold voltage and the set offset-cancelation voltage to the second input of the sample latch, wherein the set offset-cancelation voltage cancels out an offset voltage at the sample latch; and
means for inputting, in the data mode, a data signal to the first input of the sample latch.

8. The apparatus of claim 7 , wherein the threshold voltage corresponds to a target voltage level for the data signal.

9. The apparatus of claim 8 , wherein, in the data mode, the sample latch is configured to output a bit value of one or zero depending on whether a voltage of the data signal is above or below the target voltage level.

10. The apparatus of claim 7 , wherein the calibration voltage and the threshold voltage have the same magnitude and opposite polarities.

11. The apparatus of claim 7 , wherein the threshold voltage has a magnitude of at least 50 mV.

12. The apparatus of claim 7 , further comprising:
means for observing the output of the sample latch in the data mode; and
means for adjusting a gain of an amplifier until a metastable state is observed at the output of the sample latch, wherein the amplifier amplifies the data signal before the data signal is input the first input of the sample latch.

13. A receiver, comprising:
a sample latch having a first input coupled to a receive data path, and a second input;
a first digital-to-analog converter (DAC);
a second DAC;
a calibration controller, wherein, in a calibration mode, the calibration controller is configured to input a calibration voltage to the first input of the sample latch using the first DAC, to input a threshold voltage and an offset-cancelation voltage to the second input of the sample latch using the second DAC, to adjust the offset-cancelation voltage, to observe an output of the sample latch as the offset-cancelation voltage is adjusted, and to store a value of the offset-cancelation voltage at which a metastable state is observed at the output of the sample latch in a memory; and
a processor, wherein, in a data mode, the processor is configured to retrieve the value of the offset-cancelation voltage from the memory, to set the offset-cancelation voltage according to the retrieved value, and to input the threshold voltage and the set offset-cancelation voltage to the second input of the sample latch using the second DAC, wherein the set offset-cancelation voltage cancels out an offset voltage at the sample latch
wherein the sample latch receives a data signal at the first input via the receive data path in the data mode.

14. The receiver of claim 13 , wherein the threshold voltage corresponds to a target voltage level for the data signal.

15. The receiver of claim 14 , wherein, in the data mode, the sample latch is configured to output a bit value of one or zero depending on whether a voltage of the data signal is above or below the target voltage level.

16. The receiver of claim 14 , further comprising:
an amplifier configured to amplify the data signal before the data signal is received at the first input of the sample latch;
wherein, in the data mode, the processor is configured to observe the output of the sample latch, and to adjust a gain of the amplifier until a metastable state is observed at the output of the sample latch.

17. The receiver of claim 13 , wherein the calibration voltage and the threshold voltage have the same magnitude and opposite polarities.

18. The receiver of claim 13 , wherein the threshold voltage has a magnitude of at least 50 mV.

19. A method for offset calibration, comprising:
in a calibration mode, performing the steps of:
determining a plurality of values for an offset-cancelation voltage, wherein each of the plurality of values for the offset-cancelation voltage corresponds to a different target voltage level; and
storing the plurality of values for the offset-cancelation voltage in a memory; and

in a data mode, performing the steps of:
determining a target voltage level for a data signal;
retrieving one of the plurality of values for the offset-cancelation voltage corresponding to the determined target voltage level from the memory;
setting the offset-cancelation voltage according to the retrieved value;
inputting the data signal to a first input of a sample latch; and
inputting a threshold voltage and the set offset-cancelation voltage to a second input of the sample latch, wherein the set offset-cancelation voltage cancels out an offset voltage at the sample latch.

20. The method of claim 19 , wherein the threshold voltage corresponds to the determined target voltage level for the data signal.

21. The method of claim 20 , wherein, in the data mode, the sample latch is configur

Assignees

• Qualcomm Inc

Inventors

• Chen Minhan
• Arcudia Kenneth Luis

Classifications

• H04L25/0272

  Arrangements for coupling to multiple lines, e.g. for differential transmission · CPC title

• H04B1/16

  Circuits · CPC title

• H04L25/061 Primary

  providing hard decisions only; arrangements for tracking or suppressing unwanted low frequency components, e.g. removal of DC offset (removal of DC offset in coupling arrangements H04L25/029, H04L25/0296) · CPC title

• H04L25/03057

  with a recursive structure (H04L25/03031 takes precedence) · CPC title

• H04L25/0296

  Arrangements to ensure DC-balance · CPC title