Phase-locked loops (pll), including time-to-digital converter (tdc) gain calibration circuits and related methods

Patent metadata

Field	Value
Publication number	US-2024291495-A1
Application number	US-202318114847-A
Country	US
Kind code	A1
Filing date	Feb 27, 2023
Priority date	Feb 27, 2023
Publication date	Aug 29, 2024
Grant date	—

Abstract

In a calibrated phase-locked loop (PLL), a time-to-digital (TDC) converter circuit can be calibrated to a nominal gain by a calibration circuit to achieve a desired jitter response in the PLL. The TDC circuit in the PLL measures a time difference between the reference clock and a feedback signal as a number of time increments, and the calibration circuit adjusts a resolution of the measurement by adjusting the length of the time increments (i.e., resolution). In a Vernier method employed to measure the time difference, the length of a time increment is determined by a delay difference between a first delay of a first delay circuit in a first series of first delay circuits and a second delay of a second delay circuit in a second series of second delay circuits. Adjusting the resolution of the TDC circuit includes adjusting the delay difference between the first delay and the second delay.

First claim

What is claimed is:

1 . A calibrated phase-locked loop (PLL), comprising:
a PLL comprising:
a phase-frequency detector (PFD) circuit configured to:
receive a reference signal and a feedback signal; and
generate a start signal and a stop signal separated in time by a time difference between the reference signal and the feedback signal;

a time-to-digital converter (TDC) circuit configured to generate a digital control value indicating the time difference, the digital control value having a resolution;
a digitally controlled oscillator (DCO) circuit configured to generate an output clock based on the digital control value; and
a divider circuit configured to:
generate a feedback clock based on the output clock;

a calibration circuit configured to:
receive a reference clock;
generate the reference signal and the feedback signal based on the reference clock, the feedback clock, and the output clock; and
generate a resolution control signal to control a resolution of the TDC circuit.

2 . The calibrated PLL of claim 1 , the calibration circuit comprising:
a multiplier circuit configured to generate a resolution indicator as a product of the digital control value and a frequency of the output clock; and a resolution control circuit comprising a comparator configured to compare the resolution indicator and a nominal resolution indicator, wherein the calibration circuit configured to generate the resolution control signal further comprises the resolution control circuit configured to adjust the resolution control signal based on a comparison result of the comparator.

3 . The calibrated PLL of claim 2 , the resolution control circuit comprising an accumulator circuit configured to:
store the resolution control signal; and incrementally increase the resolution control signal in response to the comparison result indicating the resolution indicator is less than the nominal resolution indicator; and incrementally decrease the resolution control signal in response to the comparison result indicating the resolution indicator is more than the nominal resolution indicator.

4 . The calibrated PLL of claim 3 , the accumulator circuit comprising a least means squared (LMS) algorithm circuit.

5 . The calibrated PLL of claim 1 , the calibration circuit further comprising a frequency counter circuit configured to:
receive the output clock; receive a reference clock; and determine the frequency of the output clock based on the frequency of the reference clock.

6 . The calibrated PLL of claim 1 , the calibration circuit further configured to:
receive a calibration enable signal; in response to an operation mode in which the calibration enable signal comprises a first state:
generate the reference signal having a reference frequency of the reference clock; and
generate the feedback signal having a feedback frequency based on an output frequency of the output clock; and
in response to a calibration mode in which the calibration enable signal comprises a second state:
generate the reference signal and the feedback signal, each having a calibration frequency and a calibration time difference.

7 . The calibrated PLL of claim 6 , the calibration circuit comprising:
a phase generator comprising a state machine configured to, in the calibration mode:
generate the reference signal and the feedback signal, each having the calibration frequency of one quarter (¼) of the output frequency; and
generate the feedback signal delayed by the calibration time difference equal to one quarter (¼) of a one cycle period at the calibration frequency.

8 . The calibrated PLL of claim 1 , the TDC circuit further configured to:
receive the start signal and the stop signal; generate the digital control value as a number of time increments in the time difference between the start signal and the stop signal, wherein the resolution of the digital control value generated in the TDC circuit corresponds to one of the time increments.

9 . The calibrated PLL of claim 8 , the TDC circuit comprising:
first delay circuits coupled in a first series, wherein an output of one of the first delay circuits in the first series is coupled to an input of a next one of the first delay circuits in the first series; first capacitors, each coupled to the output of one of the first delay circuits in the first series; second delay circuits coupled in a second series, wherein an output of one of the second delay circuits in the second series is coupled to an input of a next one of the second delay circuits in the second series; and second adjustable capacitors, each coupled to the output of one of the second delay circuits in the second series, wherein:
each of the first delay circuits comprises a first delay based on a first capacitance of the first capacitor coupled to the output of the first delay circuit;
each of the second delay circuits comprises a second delay based on a second capacitance of the second adjustable capacitor coupled to the output of the second delay circuit;
each time increment of the time increments corresponds to a difference between the first delay of each of the first delay circuits and the second delay of each of the second delay circuits; and
the TDC circuit is configured to control the time increment based on the resolution control signal.

10 . The calibrated PLL of claim 9 , wherein:
the TDC circuit configured to control the time increment comprises the TDC circuit configured to adjust the second capacitance of each of the second adjustable capacitors; and the first capacitors comprise a fixed capacitance.

11 . The calibrated PLL of claim 9 , wherein:
the first capacitors comprise first adjustable capacitors; and the TDC circuit configured to control the time increment comprises the TDC circuit configured to adjust the first capacitance of each of the first adjustable capacitors and adjust the second capacitance of each of the second adjustable capacitors.

12 . A method of operating a calibrated digital phase-locked loop (PLL), comprising:
receiving a reference signal and a feedback signal; generating a start signal and a stop signal separated in time by a time difference between the reference signal and the feedback signal; generating, in a time-to-digital converter (TDC) circuit, a digital control value indicating the time difference, the digital control value having a resolution; generating an output clock based on the digital control value; generating the feedback clock based on the output clock; receiving a reference clock and generating the reference signal and the feedback signal based on the reference clock, the feedback clock, and the output clock; and generating a resolution control signal to control a resolution of the digital control value generated in the TDC circuit.

13 . The method of claim 12 , the calibration circuit comprising:
generating a resolution indicator as a product of the digital control value and a frequency of the output clock; and comparing the resolution indicator and a nominal resolution indicator, wherein generating the resolution control signal further comprises adjusting the resolution control signal based on a comparison result of the comparing.

14 . The method of claim 13 , further comprising:
storing the resolution control signal; and incrementally increasing the resolution control signal in response to the comparison result indicating the resolution indicator is less than the nominal resolution indicator; and incrementally decreasing the resolution control signal in response to the comparison result indicating the resolu

Assignees

• Microsoft Technology Licensing Llc

Inventors

• Lu Ping
• Pandita Bupesh
• Chen Minhan

Classifications

• H03L7/1077

  by changing characteristics of the phase or frequency detection means (H03L7/1072 takes precedence) · CPC title

• H03L7/099

  concerning mainly the controlled oscillator of the loop · CPC title

• H03L7/093

  using special filtering or amplification characteristics in the loop (H03L7/087 - H03L7/091 take precedence) · CPC title

• H03L7/085

  concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal (H03L7/10 takes precedence; circuits for comparing the phase or frequency of two mutually-independent oscillations H03D13/00) · CPC title

• G04F10/005

  Time-to-digital converters [TDC] (analog-to-digital converters with intermediate conversion to time or phase H03M1/50, H03M1/60) · CPC title