Peak voltage amplitude detectors tolerant to process variation and device mismatch and related methods

Patent metadata

Field	Value
Publication number	US-11953527-B2
Application number	US-202217894626-A
Country	US
Kind code	B2
Filing date	Aug 24, 2022
Priority date	Aug 24, 2022
Publication date	Apr 9, 2024
Grant date	Apr 9, 2024

Abstract

A peak detector comprises multiple small-size amplitude detection circuits coupled in parallel to signal inputs at which a signal is received from a VCO. Each amplitude detection circuit generates a voltage on an output, indicating a voltage peak or amplitude of a first signal input and a second signal input (specifically, differential output of VCO). At a given time, only one small-size amplitude detection circuit is activated to load VCO, reducing the impact on LC resonant frequency. The plurality of small-size detection circuits work sequentially, and an automatic averaging of their outputs can significantly improve the peak detector fluctuation (caused by process variation and device mismatch) compared to each single small-size amplitude detection circuit.

First claim

What is claimed is:

1. A peak detector, comprising:
a plurality of amplitude detection circuits coupled in parallel to a first signal input and a second signal input, each of the plurality of amplitude detection circuits configured to generate, on an output, a peak voltage indicating an amplitude of an input signal received on the first signal input and the second signal input;
an averaging circuit coupled to the output of each of the plurality of amplitude detection circuits, the averaging circuit configured to generate, on a peak detector output, an average voltage comprising an average of the peak voltages on the outputs of the plurality of amplitude detection circuits;
wherein each of the plurality of amplitude detection circuits comprises:
a first input switch coupled to the first signal input;
a second input switch coupled to the second signal input; and
an output switch coupled to the output.

2. The peak detector of claim 1 , each of the plurality of amplitude detection circuits comprises:
a first sense circuit configured to generate the peak voltage on the output based on the input signal received on the first input signal; and
a second sense circuit configured to generate the peak voltage on the output based on the input signal received on the second input signal.

3. The peak detector of claim 2 , wherein
the first sense circuit comprises a first transistor comprising:
a gate coupled to the first signal input;
a first source/drain coupled to a supply voltage source; and
a second source/drain coupled to the output;

the second sense circuit comprises a second transistor comprising:
a gate coupled to the second signal input;
a first source/drain coupled to the supply voltage source; and
a second source/drain coupled to the output; and

each of the plurality of amplitude detection circuits further comprises:
a capacitor coupled to the output and a reference voltage source; and
a current source coupled to the output and the reference voltage source.

4. The peak detector of claim 1 , further comprising a control circuit configured to close both of the first input switch and the second input switch in each of the plurality of amplitude detection circuits, one amplitude detection circuit at a time.

5. The peak detector of claim 1 , wherein each of the plurality of amplitude detection circuits further comprises:
a first resistor-capacitor (RC) circuit coupled to the first signal input by the first input switch; and
a second RC circuit coupled to the second signal input by the second input switch.

6. The peak detector of claim 5 , the averaging circuit comprises:
a plurality of capacitors, each coupled to the output of a corresponding one of the plurality of amplitude detection circuits; and
a plurality of averaging switches, each coupled to the outputs of two of the plurality of amplitude detection circuits,
wherein the plurality of averaging switches is coupled in series to couple each of the outputs of each of the plurality of amplitude detection circuits to the peak detector output.

7. The peak detector of claim 6 , further comprising a control circuit configured to close the plurality of averaging switches to couple the plurality of capacitors to the peak detector output.

8. The peak detector of claim 1 , further comprising:
a first resistor-capacitor (RC) circuit coupled to the first signal input and to the first input switch of each of the plurality of amplitude detection circuits; and
a second RC circuit coupled the second signal input and to the second input switch of each of the plurality of amplitude detection circuits.

9. The peak detector of claim 1 , wherein:
the plurality of amplitude detection circuits includes a plurality of odd amplitude detection circuits and a plurality of even amplitude detection circuits; and
the averaging circuit comprises:
a plurality of capacitors comprising:
a first capacitor coupled to the output of a first even amplitude detection circuit of the plurality of even amplitude detection circuits; and
a plurality of second capacitors, each coupled to the output of one of the plurality of odd amplitude detection circuits; and

a plurality of averaging switches, each coupled to the output of a corresponding one of the plurality of odd amplitude detection circuits and a corresponding one of the plurality of even amplitude detection circuits; and

the output of the first even amplitude detection circuit is coupled to the outputs of the plurality of odd amplitude detection circuits and to the peak detector output.

10. The peak detector of claim 9 , a control circuit configured to, for each of the plurality of odd amplitude detection circuits, one at a time, close the averaging switch of the plurality of averaging switches coupling the one of the plurality of second capacitors corresponding to the odd amplitude detection circuit to the first capacitor.

11. The peak detector of claim 10 , the control circuit further configured to close the plurality of averaging switches to couple the capacitors of each of the plurality of even amplitude detection circuits to the peak detector output.

12. An integrated circuit (IC), comprising:
a transmitter configured to generate a transmission signal;
a PLL comprising a voltage-controlled oscillator (VCO) configured to generate an output signal having an amplitude based on a control voltage, the PLL configured to control a frequency of the transmission signal;
a peak detector comprising:
a plurality of amplitude detection circuits coupled in parallel to a first signal input and a second signal input, each of the plurality of amplitude detection circuits configured to generate a voltage on an output indicating a voltage difference between the first signal input and the second signal input; and
an averaging circuit coupled to the output of each of the plurality of amplitude detection circuits, the averaging circuit configured to generate, on a peak detector output, an average voltage comprising an average of the voltages generated on the outputs of the plurality of amplitude detection circuits; and

a range sensor configured to:
determine whether the average voltage on the peak detector output is outside a voltage range; and
adjust the control voltage in response to determining the average voltage on the peak detector output is outside a voltage range.

13. The IC of claim 12 , wherein each of the plurality of amplitude detection circuits of the peak detector further comprises:
a source follower circuit configured to generate the voltage on the output based on a higher voltage on one of the first input and the second signal input.

14. The IC of claim 12 , wherein each of the plurality of amplitude detection circuits of the peak detector further comprises:
a first input switch coupled to the first signal input; and
a second input switch coupled to the second signal input.

15. The IC of claim 14 , further comprising a control circuit configured to close both of the first input switch and the second input switch in each of the plurality of amplitude detection circuits, one amplitude detection circuit at a time sequentially.

16. A method of detecting an amplitude in a peak detector, the peak detector comprising:
a plurality of amplitude detection circuits coupled in parallel to a first signal input and a second signal input, each of the plurality of amplitude detection circuits comprising an output;
an averaging circuit coupled to the output of each of the plurality of amplitude detection circuits; and
a peak detector output,
the method comprising:
generating,

Assignees

• Microsoft Technology Licensing Llc

Inventors

• Lu Ping
• Desai Shaishav A
• Chen Minhan

Classifications

• H03L7/099 Primary

  concerning mainly the controlled oscillator of the loop · CPC title

• H03L5/00

  Automatic control of voltage, current, or power · CPC title

• H03K5/1532

  Peak detectors (measuring characteristics of individual pulses G01R29/02) · CPC title

• G01R19/04 Primary

  Measuring peak values {or amplitude or envelope} of AC or of pulses · CPC title