Low-power, low-latency time-to-digital-converter-based serial link

Patent metadata

Field	Value
Publication number	US-10965442-B2
Application number	US-201816150123-A
Country	US
Kind code	B2
Filing date	Oct 2, 2018
Priority date	Oct 2, 2018
Publication date	Mar 30, 2021
Grant date	Mar 30, 2021

Abstract

A receiver is provided that includes a time-to-digital converter for converting a phase difference between a clock signal and a received data signal into a phase-difference digital code. The receiver also includes a logic circuit that controls a programmable delay line to delay the clock signal into a delayed clock signal by a delay that is responsive to a difference between the phase-difference code and a unit interval for the clock signal. The delayed clock signal clocks a flip-flop to register the received data signal.

First claim

We claim:

1. A receiver, comprising:
a phase detector configured to determine a phase difference between a received data signal and an input clock signal;
a time-to-digital converter configured to convert the phase difference into a phase-difference digital code and to convert a clock period of the input clock signal into a clock-period digital code;
a programmable delay line configured to delay a clock signal by a delay to form a delayed clock signal;
a flip-flop configured to be clocked by the delayed clock signal to register the received data signal; and
a logic circuit configured to control the delay for the programmable delay line responsive to a difference between the phase-difference digital code and the clock-period digital code.

2. The receiver of claim 1 , wherein the logic circuit comprises a state machine.

3. The receiver of claim 1 , further comprising:
a multiplexer configured to select between the input clock signal and a complement of the input clock signal to form a selected clock signal, wherein the logic circuit is further configured to control the selection by the multiplexer responsive to the difference between the phase-difference digital code and the clock-period digital code, and wherein the programmable delay line is further configured to delay the selected clock signal to form the delayed clock signal.

4. The receiver of claim 3 , further comprising a clock source configured to provide the input clock signal.

5. The receiver of claim 4 , wherein the clock source is a phase-locked loop.

6. The receiver of claim 3 , wherein the logic circuit is further configured to control the multiplexer to select for the input clock signal responsive to the phase-difference digital code being less than one-half of the clock-period digital code.

7. The receiver of claim 6 , wherein the logic circuit is further configured to control the multiplexer to select for the complement of the input clock signal responsive to the phase-difference digital code being greater than one-half of the clock-period digital code.

8. A method of receiving a data signal, comprising;
converting a clock period of an input clock signal into a clock-period digital code;
determining a phase difference between the data signal and the input clock signal;
converting the phase difference into a phase-difference digital code;
delaying the input clock signal by a delay responsive to the difference between the phase-difference digital code and the clock-period digital code to form a delayed clock signal;
controlling the delay responsive to a difference between the phase difference digital code and the clock-period digital code, and registering the data signal responsive to the delayed clock signal.

9. The method of claim 8 , further comprising:
selecting between an input clock signal and a complement of the input clock signal to form a selected clock signal, wherein the delaying of the input clock signal by the programmable delay responsive to the difference between the phase-difference digital code and the clock-period digital code to form the delayed clock signal comprises delaying the selected clock signal by the programmable delay.

10. The method of claim 9 , wherein the selecting between the input clock signal and the complement of the input clock signal to form the selected clock signal comprises selecting for the input clock signal responsive to the phase-difference digital code being less than one-half of the clock-period digital code.

11. The method of claim 10 , wherein the selecting between the input clock signal and the complement of the input clock signal to form the selected clock signal further comprises selecting for the complement of the input clock signal responsive to the phase-difference digital code being greater than one-half of the clock-period digital code.

12. The method of claim 8 , wherein the converting the clock period for the input clock signal into the clock-period digital code comprises converting the clock period in a time-to-digital converter.

13. The method of claim 8 , further comprising:
dividing an input clock signal by two to form a divided clock signal; and
detecting a phase difference between the divided clock signal and a complement of the divided clock signal to form a detected phase difference, wherein the converting of the clock period for the input clock signal into the clock-period digital code comprises converting the detected phase difference into the clock-period digital code.

14. A receiver, comprising:
a phase detector configured to determine a first phase difference between a received data signal and an input clock signal and a second phase difference between a divided version of the input clock signal and a complement of the divided version of the input clock signal;
means for converting the first phase difference into a phase-difference digital code and for converting the second phase difference into a clock-period digital code;
means for delaying the input clock signal into a delayed clock signal by a programmable delay responsive to a difference between the phase-difference digital code and the clock-period digital code; and
a flip-flop configured to be clocked by the delayed clock signal to register the received data signal.

15. The receiver of claim 14 , further comprising a clock source configured to provide the input clock signal.

16. The receiver of claim 15 , wherein the clock source comprises a phase-locked loop.

17. The receiver of claim 15 , wherein the receiver is integrated into a master device further comprising a transmitter configured to transmit a transmitted data signal to a slave device responsive to the input clock signal.

Assignees

• Qualcomm Inc

Inventors

• Hailu Eskinder
• Pandita Bupesh
• Boyette Jon
• Goudarzi Hadi
• Jun Yong Suk
• Zhu Zhi
• Chen Minhan

Classifications

• H04L7/046

  using a dotting sequence · CPC title

• H03K3/037

  Bistable circuits · CPC title

• H03K5/159

  Applications of delay lines not covered by the preceding subgroups · CPC title

• H04L7/10

  Arrangements for initial synchronisation · CPC title

• H04L7/0331 Primary

  with a digital phase-locked loop [PLL] processing binary samples, e.g. add/subtract logic for correction of receiver clock (H04L7/0337 takes precedence) · CPC title