Gate-all-around integrated circuit structures having insulator substrate
US-2025234646-A1 · Jul 17, 2025 · US
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Cea Stephen patents
Cea Stephen is listed as an inventor on 42 patents in our database. Major assignees and classification codes are summarized below.
| Metric | Value |
|---|---|
| Inventor | Cea Stephen |
| Total patents | 42 |
| First publication | Sep 14, 2017 |
| Latest publication | Jul 17, 2025 |
Notable patents
Publications ranked by popularity score, then publication date.
Gate-all-around integrated circuit structures having high mobility
US-12336278-B2 · Jun 17, 2025 · US
Gate-all-around integrated circuit structures having insulator substrate
US-12294006-B2 · May 6, 2025 · US
Wrap-around contact structures for semiconductor nanowires and nanoribbons
US-12176429-B2 · Dec 24, 2024 · US
Channel structures with sub-fin dopant diffusion blocking layers
US-11984449-B2 · May 14, 2024 · US
Sub-fin leakage reduction for template strained materials
US-11923412-B2 · Mar 5, 2024 · US
Wrap-around contact structures for semiconductor nanowires and nanoribbons
US-2024047566-A1 · Feb 8, 2024 · US
Transistor contact area enhancement
US-11843052-B2 · Dec 12, 2023 · US
Wrap-around contact structures for semiconductor nanowires and nanoribbons
US-11824107-B2 · Nov 21, 2023 · US
Deep source and drain for transistor structures with back-side contact metallization
US-11688780-B2 · Jun 27, 2023 · US
Recent patents
Latest publications not already listed above.
Sub-fin leakage reduction for template strained materials
US-2023187492-A1 · Jun 15, 2023 · US
Single-sided nanosheet transistors
US-2023114214-A1 · Apr 13, 2023 · US
Gate-all-around integrated circuit structures having high mobility
US-2023116170-A1 · Apr 13, 2023 · US
Transistor structures with reduced source/drain leakage through backside treatment of subfin semiconductor material
US-2023097948-A1 · Mar 30, 2023 · US
Gate-all-around integrated circuit structures having vertically discrete source or drain structures
US-2023074199-A1 · Mar 9, 2023 · US
Sub-fin leakage reduction for template strained materials
US-11600696-B2 · Mar 7, 2023 · US
Wrap-around contact structures for semiconductor nanowires and nanoribbons
US-2023068314-A1 · Mar 2, 2023 · US
Channel structures with sub-fin dopant diffusion blocking layers
US-2023043665-A1 · Feb 9, 2023 · US
Transistors with source & drain etch stop
US-2022415708-A1 · Dec 29, 2022 · US
Gate-all-around integrated circuit structures having high mobility
US-11538806-B2 · Dec 27, 2022 · US
Gate-all-around integrated circuit structures having vertically discrete source or drain structures
US-11527612-B2 · Dec 13, 2022 · US
Removal of a bottom-most nanowire from a nanowire device stack
US-11527613-B2 · Dec 13, 2022 · US
Wrap-around contact structures for semiconductor nanowires and nanoribbons
US-11527640-B2 · Dec 13, 2022 · US
Channel structures with sub-fin dopant diffusion blocking layers
US-11521968-B2 · Dec 6, 2022 · US
Multiple strain states in epitaxial transistor channel through the incorporation of stress-relief defects within an underlying seed material
US-11495683-B2 · Nov 8, 2022 · US
Stacked nanowire transistor structure with different channel geometries for stress
US-11367722-B2 · Jun 21, 2022 · US
Transistor contact area enhancement
US-2022157984-A1 · May 19, 2022 · US
Transistor contact area enhancement
US-11276780-B2 · Mar 15, 2022 · US
Multiple strain states in epitaxial transistor channel through the incorporation of stress-relief defects within an underlying seed material
US-2021257492-A1 · Aug 19, 2021 · US
Gate-all-around integrated circuit structures having insulator substrate
US-2021202534-A1 · Jul 1, 2021 · US
Major assignees
Companies most often associated with this inventor's publications.
| Assignee | Patents |
|---|---|
| Intel Corp | 42 |
Top CPC classifications
Most common classification codes across this inventor's patents.
| CPC | Patents |
|---|---|
| H10D30/024 | 35 |
| H10D62/151 | 32 |
| H10D30/62 | 32 |
| H10D30/6735 | 29 |
| H10D30/014 | 29 |