Sub-fin leakage reduction for template strained materials

Patent metadata

Field	Value
Publication number	US-11600696-B2
Application number	US-201916457347-A
Country	US
Kind code	B2
Filing date	Jun 28, 2019
Priority date	Jun 28, 2019
Publication date	Mar 7, 2023
Grant date	Mar 7, 2023

Abstract

Embodiments disclosed herein include transistor devices and methods of forming such transistor devices. In an embodiment a transistor comprises a substrate, and a fin that extends up from the substrate. In an embodiment, the fin comprises a source region, a drain region, and a channel region between the source region and the drain region. In an embodiment, the transistor further comprises and a cavity in the fin, where the cavity is below the channel region. In an embodiment, the transistor further comprises a gate stack over the fin.

First claim

What is claimed is:

1. A transistor, comprising:
a substrate;
a fin extending up from the substrate, wherein the fin comprises:
a source region;
a drain region; and
a channel region between the source region and the drain region;

a cavity in the fin, wherein the cavity is below the channel region; and
a gate stack over the fin.

2. The transistor of claim 1 , wherein the channel region comprises:
a first sidewall surface;
a second sidewall surface opposite the first sidewall surface; and
a bottom surface, wherein a first corner between the first sidewall surface and the bottom surface is rounded, and wherein a second corner between the second sidewall surface and the bottom surface is rounded.

3. The transistor of claim 2 , wherein the gate stack covers the first sidewall surface of the fin, the second sidewall surface of the fin, and a top surface of the fin, wherein the top surface is opposite from the bottom surface.

4. The transistor of claim 2 , wherein the gate stack surrounds an entire perimeter of the channel region.

5. The transistor of claim 1 , wherein the cavity is filled with an insulative material.

6. The transistor of claim 5 , wherein the insulative material is an oxide, a nitride, or an oxynitride.

7. The transistor of claim 1 , wherein the cavity extends under the source region and the drain region.

8. The transistor of claim 1 , wherein the gate stack comprises:
a gate dielectric; and
a gate electrode.

9. The transistor of claim 8 , wherein the gate stack further comprises:
a first spacer proximate to a boundary between the source region and the channel region; and
a second spacer proximate to a boundary between the drain region and the channel region.

10. The transistor of claim 1 , further comprising:
an isolation layer over the substrate and along sidewalls of the fin.

11. The transistor of claim 10 , wherein a topmost surface of the isolation layer is below a bottommost surface of the channel region.

12. The transistor of claim 1 , wherein a lattice mismatch between the source region and the channel region and between the drain region and the channel region is approximately 0.5% or greater.

13. The transistor of claim 12 , wherein the channel region comprise silicon and germanium.

14. An electronic system, comprising:
a board;
an electronic package electrically coupled to the board; and
a semiconductor die electrically coupled to the electronic package, wherein the semiconductor die comprises:
a non-planar transistor, wherein the non-planar transistor comprises:
a channel region between a source region and a drain region;
a cavity in below the channel region; and
a gate stack over at least a first surface and a second surface of the channel region.

15. The electronic system of claim 14 , wherein the non-planar transistor is a tri-gate transistor.

16. The electronic system of claim 14 , wherein the non-planar transistor is a gate all around (GAA) transistor.

Assignees

• Intel Corp

Inventors

• Mehandru Rishabh
• Cea Stephen
• Bowonder Anupama
• Nam Juhyung
• Rachmady Willy

Classifications

• H10D64/017 Primary

  using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes · CPC title

• H10D62/121

  oriented parallel to substrates · CPC title

• H10D30/6735

  having gates fully surrounding the channels, e.g. gate-all-around · CPC title

• H10D30/6213

  having rounded corners · CPC title

• H10D30/797

  being in source or drain regions, e.g. SiGe source or drain · CPC title