Channel structures with sub-fin dopant diffusion blocking layers

Patent metadata

Field	Value
Publication number	US-11521968-B2
Application number	US-201816024671-A
Country	US
Kind code	B2
Filing date	Jun 29, 2018
Priority date	Jun 29, 2018
Publication date	Dec 6, 2022
Grant date	Dec 6, 2022

Abstract

Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, integrated circuit structures having channel structures with sub-fin dopant diffusion blocking layers are described. In an example, an integrated circuit structure includes a fin having a lower fin portion and an upper fin portion. The lower fin portion includes a dopant diffusion blocking layer on a first semiconductor layer doped to a first conductivity type. The upper fin portion includes a portion of a second semiconductor layer, the second semiconductor layer on the dopant diffusion blocking layer. An isolation structure is along sidewalls of the lower fin portion. A gate stack is over a top of and along sidewalls of the upper fin portion, the gate stack having a first side opposite a second side. A first source or drain structure at the first side of the gate stack.

First claim

What is claimed is:

1. An integrated circuit structure, comprising:
a fin comprising a lower fin portion and an upper fin portion, the lower fin portion comprising a dopant diffusion blocking layer on a first semiconductor layer doped to a first conductivity type, and the upper fin portion comprising a portion of a second semiconductor layer, the second semiconductor layer on the dopant diffusion blocking layer;
an isolation structure along sidewalls of the lower fin portion, the isolation structure having an uppermost surface above an uppermost surface of the dopant diffusion blocking layer, and the isolation structure having a bottommost surface below a bottommost surface of the first semiconductor layer;
a gate stack over a top of and along sidewalls of the upper fin portion, the gate stack having a first side opposite a second side;
a first source or drain structure at the first side of the gate stack, wherein the dopant diffusion blocking layer extends vertically beneath the first source or drain structure; and
a second source or drain structure at the second side of the gate stack, wherein the dopant diffusion blocking layer extends vertically beneath the second source or drain structure, the first and second source or drain structures doped to a second conductivity type opposite the first conductivity type.

2. The integrated circuit structure of claim 1 , wherein the top surface of the isolation structure is above a bottom surface of the second semiconductor layer.

3. The integrated circuit structure of claim 1 , wherein the lower fin portion further comprises a portion of a bulk silicon substrate, the portion of the bulk silicon substrate below the fin, and the first semiconductor layer on the portion of the bulk silicon substrate.

4. The integrated circuit structure of claim 1 , wherein the first and second source or drain structures are first and second epitaxial source or drain structures embedded in the fin at the first and second sides of the gate stack, respectively.

5. The integrated circuit structure of claim 4 , wherein the first and second source or drain structures are on a recessed portion of the second semiconductor layer.

6. The integrated circuit structure of claim 4 , wherein the first and second source or drain structures are on a portion of the dopant diffusion blocking layer.

7. The integrated circuit structure of claim 4 , wherein the first and second source or drain structures are on a portion of the first semiconductor layer doped to the first conductivity type.

8. The integrated circuit structure of claim 1 , wherein the first conductivity type is N-type, and the second conductivity type is P-type.

9. The integrated circuit structure of claim 1 , wherein the first conductivity type is P-type, and the second conductivity type is N-type.

10. An integrated circuit structure, comprising:
a fin comprising a lower fin portion and an upper fin portion, the lower fin portion comprising a layer comprising carbon, the layer comprising carbon on an N-type doped semiconductor layer, and the upper fin portion comprising a portion of a semiconductor layer comprising germanium, the semiconductor layer comprising germanium on the layer comprising carbon;
an isolation structure along sidewalls of the lower fin portion, the isolation structure having an uppermost surface above an uppermost surface of the layer comprising carbon, and the isolation structure having a bottommost surface below a bottommost surface of the N-type doped semiconductor layer;
a gate stack over a top of and along sidewalls of the upper fin portion, the gate stack having a first side opposite a second side, and the gate stack comprising a P-type gate electrode;
a first source or drain structure at the first side of the gate stack, wherein the layer comprising carbon extends vertically beneath the first source or drain structure; and
a second source or drain structure at the second side of the gate stack, wherein the layer comprising carbon extends vertically beneath the second source or drain structure, and wherein the first and second source or drain structures are first and second P-type source or drain structures.

11. The integrated circuit structure of claim 10 , wherein the top surface of the isolation structure is above a bottom surface of the semiconductor layer comprising germanium.

12. The integrated circuit structure of claim 10 , wherein the lower fin portion further comprises a portion of a bulk silicon substrate, the portion of the bulk silicon substrate below the fin, and the N-type doped semiconductor layer on the portion of the bulk silicon substrate.

13. The integrated circuit structure of claim 10 , wherein the first and second source or drain structures are first and second epitaxial source or drain structures embedded in the fin at the first and second sides of the gate stack, respectively.

14. The integrated circuit structure of claim 13 , wherein the first and second source or drain structures are on a recessed portion of the semiconductor layer comprising germanium.

15. The integrated circuit structure of claim 13 , wherein the first and second source or drain structures are on a portion of the layer comprising carbon.

16. The integrated circuit structure of claim 13 , wherein the first and second source or drain structures are on a portion of the N-type doped semiconductor layer.

17. An integrated circuit structure, comprising:
a fin comprising a lower fin portion and an upper fin portion, the lower fin portion comprising a layer comprising carbon, the layer comprising carbon on a P-type doped semiconductor layer, and the upper fin portion comprising a portion of a semiconductor layer comprising a Group III-V material, the semiconductor layer comprising the Group III-V material on the layer comprising carbon;
an isolation structure along sidewalls of the lower fin portion, the isolation structure having an uppermost surface above an uppermost surface of the layer comprising carbon, and the isolation structure having a bottommost surface below a bottommost surface of the P-type doped semiconductor layer;
a gate stack over a top of and along sidewalls of the upper fin portion, the gate stack having a first side opposite a second side, and the gate stack comprising an N-type gate electrode;
a first source or drain structure at the first side of the gate stack, wherein the layer comprising carbon extends vertically beneath the first source or drain structure; and
a second source or drain structure at the second side of the gate stack, wherein the layer comprising carbon extends vertically beneath the second source or drain structure, and wherein the first and second source or drain structures are first and second N-type source or drain structures.

18. The integrated circuit structure of claim 17 , wherein the top surface of the isolation structure is above a bottom surface of the semiconductor layer comprising the Group III-V material.

19. The integrated circuit structure of claim 17 , wherein the lower fin portion further comprises a portion of a bulk silicon substrate, the portion of the bulk silicon substrate below the fin, and the P-type doped semiconductor layer on the portion of the bulk silicon substrate.

20. The integrated circuit structure of claim 17 , wherein the first and second source or drain structures are first and second epitaxial source or drain structures embedded in the fin at the first and second sides of the gate stack, respectively.

21. The integrated circuit struct

Assignees

• Intel Corp

Inventors

• Bomberger Cory
• Murthy Anand
• Cea Stephen
• Guha Biswajeet
• Bowonder Anupama
• Ghani Tahir

Classifications

• H01L29/267

  Electricity · mapped topic

• H01L27/0886 Primary

  Electricity · mapped topic

• H01L29/0649

  Electricity · mapped topic

• H01L29/0847

  Electricity · mapped topic

• H10D62/151

  of IGFETs  (of IGFETs having LDD or DDD structure H10D30/601; of thin film transistors H10D30/6713) · CPC title