Gate-all-around integrated circuit structures having high mobility

Patent metadata

Field	Value
Publication number	US-11538806-B2
Application number	US-201816143951-A
Country	US
Kind code	B2
Filing date	Sep 27, 2018
Priority date	Sep 27, 2018
Publication date	Dec 27, 2022
Grant date	Dec 27, 2022

Abstract

Gate-all-around integrated circuit structures having high mobility, and methods of fabricating gate-all-around integrated circuit structures having high mobility, are described. For example, an integrated circuit structure includes a silicon nanowire or nanoribbon. An N-type gate stack is around the silicon nanowire or nanoribbon, the N-type gate stack including a compressively stressing gate electrode. A first N-type epitaxial source or drain structure is at a first end of the silicon nanowire or nanoribbon. A second N-type epitaxial source or drain structure is at a second end of the silicon nanowire or nanoribbon. The silicon nanowire or nanoribbon has a <110> plane between the first N-type epitaxial source or drain structure and the second N-type epitaxial source or drain structure.

First claim

What is claimed is:

1. An integrated circuit structure, comprising:
a silicon nanowire above a substrate;
an N-type gate stack around the silicon nanowire, the N-type gate stack comprising a compressively stressing gate electrode;
a first N-type epitaxial source or drain structure at a first end of the silicon nanowire; and
a second N-type epitaxial source or drain structure at a second end of the silicon nanowire, wherein the silicon nanowire has a top surface above the substrate, the top surface having a <110> plane between the first N-type epitaxial source or drain structure and the second N-type epitaxial source or drain structure.

2. The integrated circuit structure of claim 1 , wherein the N-type gate stack comprises a conductive layer comprising a material selected from the group consisting of TiN, Cr, Al, V, Zr, and Nb.

3. The integrated circuit structure of claim 1 , wherein first N-type epitaxial source or drain structure and the second N-type epitaxial source or drain structure comprise phosphorous dopant impurity atoms.

4. The integrated circuit structure of claim 1 , wherein the N-type gate stack further comprises a high-k gate dielectric layer.

5. An integrated circuit structure, comprising:
a vertical arrangement of silicon nanowires above a fin;
an N-type gate stack around the vertical arrangement of silicon nanowires, the N-type gate stack comprising a compressively stressing gate electrode;
a first N-type epitaxial source or drain structure at a first end of the vertical arrangement of silicon nanowires; and
a second N-type epitaxial source or drain structure at a second end of the vertical arrangement of silicon nanowires, wherein each nanowire of the vertical arrangement of silicon nanowires has a top surface above the fin, the top surface having a <110> plane between the first N-type epitaxial source or drain structure and the second N-type epitaxial source or drain structure.

6. The integrated circuit structure of claim 5 , wherein the N-type gate stack comprises a conductive layer comprising a material selected from the group consisting of TiN, Cr, Al, V, Zr, and Nb.

7. The integrated circuit structure of claim 5 , wherein first N-type epitaxial source or drain structure and the second N-type epitaxial source or drain structure comprise phosphorous dopant impurity atoms.

8. The integrated circuit structure of claim 5 , further comprising:
a first conductive contact structure coupled to the first N-type epitaxial source or drain structure; and
a second conductive contact structure coupled to the second N-type epitaxial source or drain structure, the second conductive contact structure deeper along the fin than the first conductive contact structure.

9. The integrated circuit structure of claim 8 , wherein the first conductive contact structure is not along the fin.

10. The integrated circuit structure of claim 8 , wherein the first conductive contact structure is partially along the fin.

11. The integrated circuit structure of claim 8 , wherein the second conductive contact structure is along an entirety of the fin.

12. The integrated circuit structure of claim 8 , wherein the second conductive contact structure has an exposed surface at a bottom of the fin.

13. The integrated circuit structure of claim 5 , wherein the first and second N-type epitaxial source or drain structures are discrete first and second N-type epitaxial source or drain structures.

14. The integrated circuit structure of claim 5 , wherein the first and second N-type epitaxial source or drain structures are non-discrete first and second epitaxial N-type source or drain structures.

15. The integrated circuit structure of claim 5 , wherein the fin is a silicon fin.

16. The integrated circuit structure of claim 5 , wherein the N-type gate stack comprises a high-k gate dielectric layer.

17. An integrated circuit structure, comprising:
a silicon nanoribbon above a substrate;
an N-type gate stack around the silicon nanoribbon, the N-type gate stack comprising a compressively stressing gate electrode;
a first N-type epitaxial source or drain structure at a first end of the silicon nanoribbon; and
a second N-type epitaxial source or drain structure at a second end of the silicon nanoribbon, wherein the silicon nanoribbon has a top surface above the substrate, the top surface having a <110> plane between the first N-type epitaxial source or drain structure and the second N-type epitaxial source or drain structure.

18. The integrated circuit structure of claim 17 , wherein the N-type gate stack comprises a conductive layer comprising a material selected from the group consisting of TiN, Cr, Al, V, Zr, and Nb.

19. The integrated circuit structure of claim 17 , wherein first N-type epitaxial source or drain structure and the second N-type epitaxial source or drain structure comprise phosphorous dopant impurity atoms.

20. The integrated circuit structure of claim 17 , wherein the N-type gate stack further comprises a high-k gate dielectric layer.

21. An integrated circuit structure, comprising:
a vertical arrangement of silicon nanowires above a fin;
an N-type gate stack around the vertical arrangement of silicon nanowires, the N-type gate stack comprising a compressively stressing gate electrode;
a first N-type epitaxial source or drain structure at a first end of the vertical arrangement of silicon nanowires;
a second N-type epitaxial source or drain structure at a second end of the vertical arrangement of silicon nanowires, wherein each nanowire of the vertical arrangement of silicon nanowires has a top surface having a <110> plane between the first N-type epitaxial source or drain structure and the second N-type epitaxial source or drain structure;
a first conductive contact structure coupled to the first N-type epitaxial source or drain structure; and
a second conductive contact structure coupled to the second N-type epitaxial source or drain structure, the second conductive contact structure deeper along the fin than the first conductive contact structure.

Assignees

• Intel Corp

Inventors

• Kotlyar Roza
• Mehandru Rishabh
• Cea Stephen
• Guha Biswajeet
• Crum Dax
• Ghani Tahir

Classifications

• B82Y10/00

  Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic · CPC title

• H01L29/785

  Electricity · mapped topic

• H01L29/4966

  Electricity · mapped topic

• H01L29/0847

  Electricity · mapped topic

• H01L29/0673

  Electricity · mapped topic