Single-sided nanosheet transistors

Patent metadata

Field	Value
Publication number	US-2023114214-A1
Application number	US-202117485158-A
Country	US
Kind code	A1
Filing date	Sep 24, 2021
Priority date	Sep 24, 2021
Publication date	Apr 13, 2023
Grant date	—

Abstract

Single-sided nanosheet transistor structures comprising an upper channel material over a lower channel material. A first dielectric material is formed adjacent to a first sidewall of the upper and lower channel materials. A second dielectric material is formed adjacent to a second sidewall of the upper and lower channel materials. The first sidewall of the upper and lower channel materials is exposed by etching at least a portion of the first dielectric material. A sidewall portion of the second dielectric material may be exposed by removing sacrificial material from between the upper and lower channel materials. A single-sided gate stack may then be formed in direct contact with the first sidewall of the upper and lower channel materials, and in contact with the sidewall portion of the second dielectric material.

First claim

What is claimed is:

1 . An integrated circuit (IC) structure, comprising:
a fin comprising an upper channel material over a lower channel material; a gate insulator in direct contact with a first sidewall of the upper and lower channel materials; a gate electrode in contact with the gate insulator and adjacent to the first sidewall of each of the upper and lower channel materials, wherein the gate insulator and the gate electrode is also within a space between the upper and lower channel materials; and a dielectric material adjacent to the first sidewall and a second, opposite, sidewall of each of the upper and lower channel materials, wherein:
the dielectric material is in direct contact with the second sidewall of each of the upper and lower channel materials; and
the gate electrode and the gate insulator are between the dielectric material and the first sidewall of each of the upper and lower channel materials.

2 . The IC structure of claim 1 , wherein:
the dielectric material is a first dielectric material of a first composition; and the structure further comprises a second dielectric material of a second composition in direct contact with a first sidewall of a base of the fin, below the lower channel semiconductor material; the gate electrode is over the second dielectric material; and the second dielectric material is between the first dielectric material and the base of the fin.

3 . The IC structure of claim 2 , wherein the second dielectric material has a lateral thickness, normal from the first sidewall of the base of the fin, and wherein the first dielectric material is separated from the first sidewall of the upper and lower channel materials by no more than the lateral thickness.

4 . The IC structure of claim 1 , wherein fin is a first fin and the gate electrode is a first gate electrode, and the IC structure further comprises:
a pair of second fins adjacent to the first fin, wherein each of the second fins comprise the upper channel material over the lower channel material; and a second gate electrode between the pair of second fins, and adjacent to a gate insulator that is in direct contact with an interior sidewall of each of the upper and lower channel materials of both second fins, wherein:
the second gate electrode is between the upper and lower channel materials of both second fins; and
the dielectric material is adjacent to, and in contact with, an exterior sidewall of each of the upper and lower channel materials of both second fins.

5 . The IC structure of claim 4 , wherein the pair of second fins are spaced apart from each other by a first distance, and one of the pair of second fins nearest to the first fin is spaced apart from the first fin by a second distance, larger than the first distance.

6 . The IC structure of claim 4 , wherein:
the dielectric material is a first dielectric material of a first composition; and the IC structure further comprises a second dielectric material of a second composition adjacent to, and in direct contact with, a first sidewall of a base of the first fin and an interior sidewall of a base of each of the second fins; and both the first and second gate electrodes are over the second dielectric material.

7 . The IC structure of claim 1 , further comprising a source and a drain, wherein each of the source and the drain further comprises:
impurity doped semiconductor material coupled to at least one of the upper or lower channel materials; and a contact metal in direct contact with a first sidewall of the impurity doped semiconductor material, wherein the dielectric material is in direct contact with a second, opposite, sidewall of the impurity doped semiconductor material.

8 . The IC structure of claim 1 , wherein:
the upper and lower channel materials comprise silicon; the dielectric material silicon and oxygen; the gate electrode comprises a metal; and the gate insulator comprises a metal and oxygen.

9 . A computer platform, comprising:
electronic memory circuitry to store data; and processor circuitry coupled to the electronic memory circuitry, wherein at least one of the electronic memory circuitry or the processor circuitry further comprises:
a fin comprising an upper channel material over a lower channel material;
a gate insulator adjacent to, and in direct contact with, a first sidewall of each of the upper and lower channel materials;
a gate electrode in contact with the gate insulator and adjacent to the first sidewall of each of the upper and lower channel materials; wherein the gate insulator and the gate electrode are also within a space between the upper and lower channel materials; and
a dielectric material adjacent to both the first sidewall and a second, opposite, sidewall of each of the upper and lower channel materials, wherein;
the dielectric material is in direct contact with the second sidewall of each of the upper and lower channel materials; and
the gate electrode and the gate insulator are between the dielectric material and the first sidewall of each of the upper and lower channel materials.

10 . The computer platform of claim 9 , further comprising:
a battery coupled to at least the processor circuitry.

11 . A method of fabricating an integrated circuit (IC) structure, comprising:
receiving a workpiece with a fin, the fin comprising an upper channel material over a lower channel material and a sacrificial material therebetween; forming a first dielectric material adjacent to a first sidewall of the upper and lower channel materials; forming a second dielectric material adjacent to a second sidewall of the upper and lower channel materials; exposing the first sidewall of the upper and lower channel materials by etching at least a portion of the first dielectric material; exposing a sidewall portion of the second dielectric material by removing the sacrificial material from between the upper and lower channel materials; and forming a gate stack in direct contact with the first sidewall of the upper and lower channel materials, and in contact with the sidewall portion of the second dielectric material.

12 . The method of claim 11 , wherein forming the first dielectric material adjacent to the first sidewall of the upper and lower channel materials further comprises:
depositing a first dielectric material over the fin, the first dielectric material adjacent to both a first sidewall of the fin and a second, opposite, sidewall of the fin; and retaining the first dielectric material adjacent to the first sidewall of the fin while removing the first dielectric material from the second sidewall of the fin.

13 . The method of claim 12 , wherein forming the second dielectric material adjacent to the second sidewall of the upper and lower channel materials further comprises:
depositing the second dielectric material over the first dielectric material and adjacent to the second sidewall of the fin; and planarizing the second dielectric material with a top of the first dielectric material.

14 . The method of claim 13 , wherein the etching of at least a portion of the first dielectric material further comprises isotropically etching through a thickness of the first dielectric material adjacent to the first sidewall of the first and second channel materials.

15 . The method of claim 11 wherein the channel material comprises silicon and wherein removing the sacrificial material from between the upper and lower channel materials further comprises etching the sacrificial material with an etch process selective to compositions comprising more Ge than the upper

Assignees

• Intel Corp

Inventors

• Cea Stephen
• Guha Biswajeet
• Guler Leonard
• Ghani Tahir
• Ma Sean

Classifications

• H10D30/024

  of fin field-effect transistors [FinFET] · CPC title

• H10D30/014

  of FETs having zero-dimensional [0D] or one-dimensional [1D] channels, e.g. quantum wire FETs, single-electron transistors [SET] or Coulomb blockade transistors · CPC title

• H10D30/6735 Primary

  having gates fully surrounding the channels, e.g. gate-all-around · CPC title

• H10D62/121 Primary

  oriented parallel to substrates · CPC title

• H10D30/62

  Fin field-effect transistors [FinFET] · CPC title