Removal of a bottom-most nanowire from a nanowire device stack

Patent metadata

Field	Value
Publication number	US-11527613-B2
Application number	US-202117145114-A
Country	US
Kind code	B2
Filing date	Jan 8, 2021
Priority date	Mar 30, 2017
Publication date	Dec 13, 2022
Grant date	Dec 13, 2022

Abstract

An apparatus is provided which comprises: a plurality of nanowire transistors stacked vertically, wherein each nanowire transistor of the plurality of nanowire transistors comprises a corresponding nanowire of a plurality of nanowires; and a gate stack, wherein the gate stack fully encircles at least a section of each nanowire of the plurality of nanowires.

First claim

We claim:

1. A method comprising:
forming a stack of nanowires, the stack of nanowires comprising a nanowire that is attached to a substrate, and one or more nanowires that are not attached to the substrate;
forming a gate stack, wherein the gate stack wraps around at least a corresponding section of each nanowire of the one or more nanowires, and partially wraps around the attached nanowire; and
removing the nanowire that is attached to the substrate, without removing any nanowire of the one or more nanowires.

2. The method of claim 1 , comprising:
encapsulating the stack of nanowires within an encapsulant, wherein removing the attached nanowire comprises:
removing the substrate to reveal the attached nanowire through the encapsulant;
removing the attached nanowire to form a trench within the encapsulant; and
filling the trench with a gap fill material.

3. An apparatus comprising:
a layer comprising a dielectric material;
a source region and a drain region;
one or more bodies comprising semiconductor material extending from the source region to the drain region, the one or more bodies stacked vertically above the layer;
a gate stack at least in part wrapping around at least one body of the one or more bodies; and
a dielectric structure on the layer, wherein the gate stack is on two or more surfaces of the dielectric structure.

4. The apparatus of claim 3 , wherein the dielectric structure has a bottom surface, a top surface opposite the bottom surface, and one or more side surfaces between the top and bottom surfaces, wherein the gate stack is on the top and side surfaces of the dielectric structure, and wherein the bottom surface of the dielectric structure is on the layer.

5. The apparatus of claim 3 , wherein the gate stack contacts multiple surfaces of the dielectric structure but not all surfaces of the dielectric structure, and the layer contacts at least one other surface of the dielectric structure.

6. The apparatus of claim 3 , wherein the gate stack is on three sides of the dielectric structure, and a fourth side of the dielectric structure is on the layer.

7. The apparatus of claim 3 , wherein the dielectric structure extends laterally between the source and drain regions.

8. The apparatus of claim 3 , wherein none of the one or more bodies is in direct contact with the layer.

9. The apparatus of claim 3 , wherein the gate stack fully wraps around at least a corresponding section of each body of the one or more bodies.

10. The apparatus of claim 3 , wherein the one or more bodies comprises a plurality of vertically stacked nanoribbons or a plurality of vertically stacked nanowires.

11. The apparatus of claim 3 , wherein the layer and the dielectric structure are compositionally different and/or distinct from one another.

12. The apparatus of claim 3 , wherein the structure comprises a dielectric material.

13. The apparatus of claim 3 , wherein the apparatus is part of a processor.

14. The apparatus of claim 13 , wherein the processor is coupled to a memory.

15. A system comprising:
a memory;
an antenna; and
a processor coupled to the memory and the antenna, the processor including a device comprising
a source region and a drain region,
one or more bodies comprising semiconductor material extending from the source region to the and drain region,
a gate stack at least in part wrapping around each body of the one or more bodies, and
a dielectric structure including a first surface, a second surface, and one or more side surfaces between the first and second surfaces, wherein the gate stack is on the first surface and the one or more side surfaces of the dielectric structure, and not on the second surface of the dielectric structure.

16. The system of claim 15 , wherein the device further comprises:
a layer comprising a dielectric material,
wherein the one or more bodies are above the layer and not in direct contact with the layer, and wherein the second surface of the dielectric structure is on the layer.

17. The system of claim 15 , wherein the dielectric structure is compositionally distinct from the layer.

18. The system of claim 15 , wherein the device further comprises:
a dielectric layer on one or more sides of the gate stack, wherein the dielectric layer and the dielectric structure are compositionally the same.

19. The system of claim 15 , wherein the gate stack fully wraps around a corresponding section of each body of the one or more bodies, and the gate stack partially and not fully wraps around a corresponding section of the dielectric structure.

20. The system of claim 15 , wherein the one or more bodies comprises a plurality of vertically stacked nanoribbons or nanowires.

Assignees

• Intel Corp

Inventors

• Lilak Aaron
• Keys Patrick
• Ma Sean
• Cea Stephen
• Mehandru Rishabh

Classifications

• H10P95/062

  involving a dielectric removal step · CPC title

• H10P95/11

  Separation of active layers from substrates · CPC title

• H10P50/642

  Chemical etching · CPC title

• H10W74/111

  the semiconductor body being completely enclosed · CPC title

• H10W74/019

  using temporary auxiliary substrates (H10W74/017 takes precedence) · CPC title