Transistor contact area enhancement

Patent metadata

Field	Value
Publication number	US-11276780-B2
Application number	US-201816024724-A
Country	US
Kind code	B2
Filing date	Jun 29, 2018
Priority date	Jun 29, 2018
Publication date	Mar 15, 2022
Grant date	Mar 15, 2022

Abstract

A semiconductor device includes a semiconductor body that includes a surface and a first region and a second region formed in the semiconductor body, where a channel region is located between the first region and the second region, and where the second region includes a sub-region that includes a blanket dopant; a first conductive contact on the surface of the semiconductor body above the first region; a semiconductor-on-insulator (SOI) at a bottom of the first region; and a pocket channel dopant (PCD) formed in the channel, where a first portion of the PCD is adjacent to a first portion of the SOI; and a second conductive contact on a bottom portion of the sub-region, where a first portion of the second conductive contact is adjacent to a second portion of the SOI, and a second portion of the second conductive contact is adjacent to a second portion of the PCD.

First claim

What is claimed is:

1. A semiconductor device, comprising:
a semiconductor body that includes a surface;
a first region and a second region formed in the semiconductor body, wherein a channel region is located between the first region and the second region, and wherein the second region includes a sub-region that includes a blanket dopant;
a first conductive contact on the surface of the semiconductor body above the first region;
a semiconductor-on-insulator (SOI) at a bottom of the first region;
a pocket channel dopant (PCD) formed in the channel, wherein a first portion of the PCD is adjacent to a first portion of the SOI; and
a second conductive contact on a bottom portion of the sub-region, wherein a first portion of the second conductive contact is adjacent to a second portion of the SOI, and wherein a second portion of the second conductive contact is adjacent to a second portion of the PCD.

2. The semiconductor device of claim 1 , wherein the first region is a source region and the second region is a drain region.

3. The semiconductor device of claim 1 , wherein the first region is a drain region and the second region is a source region.

4. The semiconductor device of claim 1 , wherein the blanket dopant is phosphorus.

5. The semiconductor device of claim 1 , wherein the blanket dopant is boron.

6. The semiconductor device of claim 1 , wherein the blanket dopant has a height between 5 nanometers (nm) and 100 nm.

7. The semiconductor device of claim 1 , wherein the SOI has a height between 5 nm and 115 nm.

8. The semiconductor device of claim 1 , wherein the PCD is phosphorus.

9. The semiconductor device of claim 1 , wherein the PCD is boron.

10. A semiconductor device, comprising:
a semiconductor body that includes a surface;
a first region and a second region formed in the semiconductor body, wherein a channel region is located between the first region and the second region, and wherein the second region includes a sub-region that includes a blanket dopant;
a first conductive contact on the surface of the semiconductor body above the first region;
a leakage barrier; and
a second conductive contact on a bottom portion of the sub-region, wherein at least a portion of the second conductive contact is adjacent to at least a portion of the leakage barrier.

11. The semiconductor device of claim 10 , wherein the first region is a source region and the second region is a drain region.

12. The semiconductor device of claim 10 , wherein the blanket dopant is phosphorus or boron.

13. The semiconductor device of claim 10 , wherein the leakage barrier is a semiconductor-on-insulator (SOI), wherein the SOI is at a bottom of the first region.

14. The semiconductor device of claim 10 , wherein the leakage barrier is a pocket channel dopant (PCD) formed in the channel.

15. The semiconductor device of claim 14 , wherein the PCD is phosphorus or boron.

16. The semiconductor device of claim 10 , wherein the leakage barrier comprises:
an SOI, wherein the SOI is at a bottom the first region; and
a PCD formed in the channel, wherein a first portion of the PCD is adjacent to a first portion of the SOI, a second portion of the SOI is adjacent to a first portion of the second conductive contact, and a second portion of the PCD is adjacent to a second portion of the second conductive contact.

17. The semiconductor device of claim 16 , wherein the PCD is phosphorus or boron.

18. A system, comprising:
a memory; and
a processor coupled with the memory, wherein the processor includes a semiconductor device comprising:
a semiconductor body that includes a surface;
a first region and a second region formed in the semiconductor body, wherein a channel region is located between the first region and the second region, and wherein the second region includes a sub-region that includes a blanket dopant;
a first conductive contact on the surface of the semiconductor body above the first region;
a semiconductor-on-insulator (SOI) at a bottom of the first region;
a pocket channel dopant (PCD) formed in the channel, wherein the PCD is adjacent to a first portion of the SOI; and
a second conductive contact on a bottom portion of the sub-region, wherein a first portion of the second conductive contact is adjacent to a second portion of the SOI, and wherein a second portion of the second conductive contact is adjacent to a second portion of the PCD.

19. The system of claim 18 , wherein the first region is a source region and the second region is a drain region.

20. The system of claim 18 , wherein the blanket dopant is phosphorus or boron.

21. The system of claim 18 , wherein the PCD is phosphorus or boron.

22. A method, comprising:
forming a semiconductor body that includes a surface;
forming a first region and a second region in the semiconductor body, wherein a channel region is defined in the semiconductor body between the first region and the second region;
providing a blanket dopant in a sub-region of the second region;
forming a first conductive contact on the surface of the semiconductor body above the first region;
forming a semiconductor-on-insulator (SOI) at a bottom of the first region;
providing a pocket channel dopant (PCD) in the channel, wherein a first portion of the PCD is adjacent to a first portion of the SOI; and
forming a second conductive contact on a bottom portion of the sub-region, wherein a first portion of the second conductive contact is adjacent to a second portion of the SOI and a second portion of the second conductive contact is adjacent to a second portion of the PCD.

23. The method of claim 22 , wherein the first region is a source region and the second region is a drain region.

24. The method of claim 22 , wherein the blanket dopant is phosphorus or boron.

25. The method of claim 22 , wherein the PCD is phosphorus or boron.

Assignees

• Intel Corp

Inventors

• Mehandru Rishabh
• Ghani Tahir
• Cea Stephen

Classifications

• H10D62/314

  having vertical doping variations  (vertical IGFETs H10D30/63) · CPC title

• H10D62/151

  of IGFETs  (of IGFETs having LDD or DDD structure H10D30/601; of thin film transistors H10D30/6713) · CPC title

• H10D62/116

  adjoining the input or output regions of field-effect devices, e.g. adjoining source or drain regions · CPC title

• H10D30/6219

  characterised by the source or drain electrodes · CPC title

• H10D30/024

  of fin field-effect transistors [FinFET] · CPC title