Gate-all-around integrated circuit structures having vertically discrete source or drain structures

Patent metadata

Field	Value
Publication number	US-11527612-B2
Application number	US-201816146778-A
Country	US
Kind code	B2
Filing date	Sep 28, 2018
Priority date	Sep 28, 2018
Publication date	Dec 13, 2022
Grant date	Dec 13, 2022

Abstract

Gate-all-around integrated circuit structures having vertically discrete source or drain structures, and methods of fabricating gate-all-around integrated circuit structures having vertically discrete source or drain structures, are described. For example, an integrated circuit structure includes a vertical arrangement of horizontal nanowires. A gate stack is around the vertical arrangement of horizontal nanowires. A first epitaxial source or drain structure is at a first end of the vertical arrangement of horizontal nanowires, the first epitaxial source or drain structure including vertically discrete portions aligned with the vertical arrangement of horizontal nanowires. A second epitaxial source or drain structure is at a first end of the vertical arrangement of horizontal nanowires, the second epitaxial source or drain structure including vertically discrete portions aligned with the vertical arrangement of horizontal nanowires.

First claim

What is claimed is:

1. An integrated circuit structure, comprising:
a vertical arrangement of horizontal nanowires;
a gate stack around the vertical arrangement of horizontal nanowires;
a first epitaxial source or drain structure at a first end of the vertical arrangement of horizontal nanowires, the first epitaxial source or drain structure comprising vertically discrete portions aligned with the vertical arrangement of horizontal nanowires, wherein the vertically discrete portions of the first epitaxial source or drain structure do not extend vertically beneath the gate stack;
a second epitaxial source or drain structure at a second end of the vertical arrangement of horizontal nanowires, the second epitaxial source or drain structure comprising vertically discrete portions aligned with the vertical arrangement of horizontal nanowires, wherein the vertically discrete portions of the second epitaxial source or drain structure do not extend vertically beneath the gate stack;
a sub-fin structure beneath the vertical arrangement of horizontal nanowires and beneath the first and second epitaxial source or drain structures;
a first conductive contact structure surrounding the vertically discrete portions of the first epitaxial source or drain structure; and
a second conductive contact structure surrounding the vertically discrete portions of the second epitaxial source or drain structure, wherein the first and second conductive contact structures are a pair of asymmetric conductive contact structures.

2. The integrated circuit structure of claim 1 , further comprising:
a sub-fin isolation structure between the sub-fin structure and the first and second epitaxial source or drain structures.

3. The integrated circuit structure of claim 1 , wherein one of the first and second conductive contact structures is a backside contact structure.

4. The integrated circuit structure of claim 1 , wherein the first and second epitaxial source or drain structures are compressive-stressing source or drain structures.

5. The integrated circuit structure of claim 1 , wherein the first and second epitaxial source or drain structures are tensile-stressing source or drain structures.

6. The integrated circuit structure of claim 1 , wherein the gate stack comprises a high-k gate dielectric layer and a metal gate electrode.

7. An integrated circuit structure, comprising:
a vertical arrangement of horizontal nanowires;
a gate stack around the vertical arrangement of horizontal nanowires;
a first epitaxial source or drain structure at a first end of the vertical arrangement of horizontal nanowires, the first epitaxial source or drain structure comprising vertically discrete portions aligned with the vertical arrangement of horizontal nanowires;
a second epitaxial source or drain structure at a first end of the vertical arrangement of horizontal nanowires, the second epitaxial source or drain structure comprising vertically discrete portions aligned with the vertical arrangement of horizontal nanowires;
a sub-fin structure beneath the vertical arrangement of horizontal nanowires and beneath the first and second epitaxial source or drain structures;
a first conductive contact structure surrounding the vertically discrete portions of the first epitaxial source or drain structure; and
a second conductive contact structure surrounding the vertically discrete portions of the second epitaxial source or drain structure, wherein the first and second conductive contact structures are a pair of asymmetric conductive contact structures.

8. The integrated circuit structure of claim 7 , wherein one of the first and second conductive contact structures is a backside contact structure.

9. A computing device, comprising:
a board; and
a component coupled to the board, the component including an integrated circuit structure, comprising:
a vertical arrangement of horizontal nanowires;
a gate stack around the vertical arrangement of horizontal nanowires;
a first epitaxial source or drain structure at a first end of the vertical arrangement of horizontal nanowires, the first epitaxial source or drain structure comprising vertically discrete portions aligned with the vertical arrangement of horizontal nanowires, wherein the vertically discrete portions of the first epitaxial source or drain structure do not extend vertically beneath the gate stack;
a second epitaxial source or drain structure at a second end of the vertical arrangement of horizontal nanowires, the second epitaxial source or drain structure comprising vertically discrete portions aligned with the vertical arrangement of horizontal nanowires, wherein the vertically discrete portions of the second epitaxial source or drain structure do not extend vertically beneath the gate stack;
a sub-fin structure beneath the vertical arrangement of horizontal nanowires and beneath the first and second epitaxial source or drain structures;
a first conductive contact structure surrounding the vertically discrete portions of the first epitaxial source or drain structure; and
a second conductive contact structure surrounding the vertically discrete portions of the second epitaxial source or drain structure, wherein the first and second conductive contact structures are a pair of asymmetric conductive contact structures.

10. The computing device of claim 9 , further comprising:
a memory coupled to the board.

11. The computing device of claim 9 , further comprising:
a communication chip coupled to the board.

12. The computing device of claim 9 , wherein the component is a packaged integrated circuit die.

13. The computing device of claim 9 , wherein the component is selected from the group consisting of a processor, a communications chip, and a digital signal processor.

Assignees

• Intel Corp

Inventors

• Glass Glenn
• Murthy Anand
• Guha Biswajeet
• Crum Dax M
• Ma Sean
• Ghani Tahir
• Ghose Susmita
• Cea Stephen
• Mehandru Rishabh

Classifications

• H10P72/74

  using temporarily an auxiliary support · CPC title

• H10P52/402

  of semiconductor materials · CPC title

• H10P50/642

  Chemical etching · CPC title

• H10P14/3462

  Nanowires · CPC title

• H10P14/3411

  Silicon, silicon germanium or germanium · CPC title