Multiple strain states in epitaxial transistor channel through the incorporation of stress-relief defects within an underlying seed material

Patent metadata

Field	Value
Publication number	US-11495683-B2
Application number	US-202016795473-A
Country	US
Kind code	B2
Filing date	Feb 19, 2020
Priority date	Feb 19, 2020
Publication date	Nov 8, 2022
Grant date	Nov 8, 2022

Abstract

Multiple strain states in epitaxial transistor channel material may be achieved through the incorporation of stress-relief defects within a seed material. Selective application of strain may improve channel mobility of one carrier type without hindering channel mobility of the other carrier type. A transistor structure may have a heteroepitaxial fin including a first layer of crystalline material directly on a second layer of crystalline material. Within the second layer, a number of defected regions of a threshold minimum dimension are present, which induces the first layer of crystalline material to relax into a lower-strain state. The defected regions may be introduced selectively, for example a through a masked impurity implantation, so that the defected regions may be absent in some transistor structures where a higher-strain state in the first layer of crystalline material is desired.

First claim

What is claimed is:

1. An integrated circuit (IC) structure, comprising:
a first transistor structure comprising a first fin heterostructure including a first layer of crystalline material over a second layer of crystalline material, wherein the first layer of crystalline material has a first majority atom composition comprising at least one of Si and Ge, and wherein the second layer of crystalline material has a second majority atom composition comprising at least one of Si and Ge; and
a second transistor structure comprising a second fin heterostructure including the first layer of crystalline material over the second layer of crystalline material, wherein, within the second layer, a number of defected regions of a threshold minimum dimension larger than a point defect varies between the first fin heterostructure and the second fin heterostructure.

2. The IC structure of claim 1 , wherein the second layer has a thickness between the first layer and an underlying substrate material, and wherein the defected regions are interspersed within the second layer, and most prevalent within a band of the second layer that is substantially parallel to a plane of the substrate material, the band occupying less than the thickness of the second layer.

3. The IC structure of claim 1 , wherein:
a channel region of both the first and second transistor structures comprise the first layer of crystalline material;
the first transistor structure further comprises a first source and drain material of a first conductivity type coupled to the first layer of crystalline material and on opposite sides of a first gate stack;
the second transistor structure further comprises a second source and drain material of a second conductivity type coupled to the first layer of crystalline material and on opposite sides of a second gate stack.

4. The IC structure of claim 1 , wherein the first transistor structure is of a first conductivity type, and the second transistor structure is of a second conductivity type, complementary to the first conductivity type.

5. The IC structure of claim 1 , wherein, within the second layer, a concentration of an impurity varies between the first fin heterostructure and the second fin heterostructure.

6. The IC structure of claim 5 , wherein the impurity comprises at least one of argon, xenon, silicon, nitrogen, fluorine or germanium, indium, or antimony.

7. The IC structure of claim 6 , wherein:
the first transistor is an NMOS device, the second transistor is a PMOS device, and the impurity is antimony; or
the first transistor is an PMOS device, the second transistor is a NMOS device, and the impurity comprises fluorine or indium.

8. The IC structure of claim 5 , wherein, within the second layer, the impurity present within the second fin heterostructure is absent from the first fin heterostructure.

9. The IC structure of claim 1 , wherein the first majority atom composition comprises more Ge than the second majority atom composition.

10. The IC structure of claim 1 , wherein, the first layer of crystalline material has a first lattice spacing, and the second layer of crystalline material has a second lattice spacing, and wherein the first lattice spacing is more closely matched to the second lattice spacing within the first fin heterostructure than within the second fin heterostructure.

11. The IC structure of claim 1 , further comprising:
a first gate stack adjacent to a first sidewall of the first fin heterostructure, the first sidewall comprising the first layer of crystalline material;
a first source and drain semiconductor material coupled to the first layer of crystalline material and on opposite sides of the first gate stack, wherein the first source and drain semiconductor material is a first conductivity type;
a second gate stack adjacent to a second sidewall of the second fin heterostructure, the second sidewall comprising the first layer of crystalline material; and
a second source and drain semiconductor material coupled to the first layer of crystalline material and on opposite sides of the second gate stack, wherein the second source and drain semiconductor material is a second conductivity type, complementary to the first conductivity type.

12. The IC structure of claim 11 , wherein:
the first layer of crystalline material comprises Si X Ge 1-X , and x is less than 0.8;
the second layer of crystalline material comprises Si with less Ge than the first layer;
the first conductivity type is p-type; and
the second conductivity type is n-type.

13. The IC structure of claim 11 , wherein:
the second layer of crystalline material comprises Si X Ge 1-X , and x is less than 0.8;
the first layer of crystalline material comprises Si with less Ge than the second layer;
the first conductivity type is n-type; and
the second conductivity type is p-type.

14. The IC structure of claim 1 , wherein:
the first fin heterostructure further comprises a third layer of crystalline material on the first layer, the third layer having a third majority atom composition, different than the first majority atom composition; and
the second fin heterostructure further comprises a fourth layer of crystalline material on the first layer, the fourth layer having a fourth majority atom composition, different than both the first majority atom composition and the third majority atom composition.

15. The IC structure of claim 14 , further comprising:
a first gate stack adjacent to a first sidewall of the first fin heterostructure, the first sidewall comprising the third layer of crystalline material;
a first source and drain semiconductor material coupled to the third layer of crystalline material and on opposite sides of the first gate stack, wherein the first source and drain semiconductor material is of a first conductivity type;
a second gate stack adjacent to a second sidewall of the second fin heterostructure, the second sidewall comprising the fourth layer of crystalline material; and
a second source and drain semiconductor material coupled to the fourth layer of crystalline material and on opposite sides of the second gate stack, wherein the second source and drain semiconductor material is of a second conductivity type, complementary to the first conductivity type.

16. The IC structure of claim 15 , wherein:
the first layer of crystalline material comprises Si X Ge 1-X , and x is at least 0.5;
the second layer of crystalline material comprises substantially pure Si;
the third layer of crystalline material comprises Si y Ge 1-y , and y is less than x;
the fourth layer of crystalline material comprises Si z Ge 1-z , and z is more than x;
the first conductivity type is p-type; and
the second conductivity type is n-type.

17. An integrated circuit (IC) structure, comprising:
a PMOS transistor structure comprising:
a first fin structure including a pseudomorphic layer of crystalline Si x Ge 1-x material directly on a crystalline base layer having a different Ge concentration than the pseudomorphic layer;
a first gate stack adjacent to a sidewall of first fin structure, and in contact with the pseudomorphic layer of the crystalline Si x Ge 1-x material; and
a p-type source and p-type drain semiconductor material coupled to the pseudomorphic layer of the crystalline Si x Ge 1-x material, and on opposite sides of the first gate stack;

an NMOS transistor structure comprising:
a second fin structure including a metamorphic layer of the crystalline Si x Ge 1-x material directly on the crystalline base layer;
a second gate stack adjacent to a sidewa

Assignees

• Intel Corp

Inventors

• Lilak Aaron
• Keys Patrick
• Hasan Sayed
• Cea Stephen
• Bowonder Anupama

Classifications

• H10P14/2905

  Silicon, silicon germanium or germanium · CPC title

• H01L29/66803

  Electricity · mapped topic

• H01L29/086

  Electricity · mapped topic

• H01L29/165

  Electricity · mapped topic

• H01L29/7378

  Electricity · mapped topic