Wrap-around contact structures for semiconductor nanowires and nanoribbons

Patent metadata

Field	Value
Publication number	US-11527640-B2
Application number	US-201916238978-A
Country	US
Kind code	B2
Filing date	Jan 3, 2019
Priority date	Jan 3, 2019
Publication date	Dec 13, 2022
Grant date	Dec 13, 2022

Abstract

Wrap-around contact structures for semiconductor nanowires and nanoribbons, and methods of fabricating wrap-around contact structures for semiconductor nanowires and nanoribbons, are described. In an example, an integrated circuit structure includes a semiconductor nanowire above a first portion of a semiconductor sub-fin. A gate structure surrounds a channel portion of the semiconductor nanowire. A source or drain region is at a first side of the gate structure, the source or drain region including an epitaxial structure on a second portion of the semiconductor sub-fin, the epitaxial structure having substantially vertical sidewalls in alignment with the second portion of the semiconductor sub-fin. A conductive contact structure is along sidewalls of the second portion of the semiconductor sub-fin and along the substantially vertical sidewalls of the epitaxial structure.

First claim

What is claimed is:

1. An integrated circuit structure, comprising:
a semiconductor nanowire above a first portion of a semiconductor sub-fin, the semiconductor sub-fin having a first lateral width;
a gate structure surrounding a channel portion of the semiconductor nanowire;
a source or drain region at a first side of the gate structure, the source or drain region comprising an epitaxial structure on a second portion of the semiconductor sub-fin, the epitaxial structure having substantially vertical sidewalls in alignment with the second portion of the semiconductor sub-fin, and the epitaxial structure having a second lateral width, the second lateral width substantially the same as the first lateral width; and
a conductive contact structure along sidewalls of the second portion of the semiconductor sub-fin and along the substantially vertical sidewalls of the epitaxial structure.

2. The integrated circuit structure of claim 1 , wherein the epitaxial structure comprises a flat surface distal from the second portion of the semiconductor sub-fin, and wherein the conductive contact structure is further on the flat surface.

3. The integrated circuit structure of claim 1 , wherein the epitaxial structure comprises a pair of facets that meet at a center point, and wherein the conductive contact structure is further on the pair of facets.

4. The integrated circuit structure of claim 1 , further comprising:
a pair of dielectric spacers along sidewalls of the conductive contact structure.

5. The integrated circuit structure of claim 1 , further comprising:
a second source or drain region at a second side of the gate structure, the second source or drain region comprising a second epitaxial structure on a third portion of the semiconductor sub-fin, the second epitaxial structure having substantially vertical sidewalls in alignment with the third portion of the semiconductor sub-fin; and
a second conductive contact structure along sidewalls of the third portion of the semiconductor sub-fin and along the substantially vertical sidewalls of the second epitaxial structure.

6. The integrated circuit structure of claim 1 , further comprising:
a second source or drain region at a second side of the gate structure, the second source or drain region comprising a second epitaxial structure on a third portion of the semiconductor sub-fin, the second epitaxial structure having non-vertical sidewalls extending laterally beyond the third portion of the semiconductor fin.

7. The integrated circuit structure of claim 6 , further comprising:
a pair of dielectric spacers along the second epitaxial structure and the third portion of the semiconductor sub-fin, wherein points of the non-vertical sidewalls of the second epitaxial structure are in contact with the pair of dielectric spacers.

8. The integrated circuit structure of claim 1 , wherein the epitaxial structure comprises a semiconductor material different than the semiconductor sub-fin and different than the semiconductor nanowire.

9. The integrated circuit structure of claim 1 , wherein the gate structure comprises a high-k dielectric layer, and a gate electrode comprising a metal.

10. The integrated circuit structure of claim 1 , further comprising:
a dielectric plug on a surface of the second portion of the semiconductor sub-fin opposite the epitaxial structure.

11. The integrated circuit structure of claim 10 , wherein the conductive contact structure is further along sidewalls of the dielectric plug.

12. An integrated circuit structure, comprising:
a semiconductor nanowire above a first portion of a semiconductor sub-fin, the semiconductor sub-fin having a first lateral width;
a gate structure surrounding a channel portion of the semiconductor nanowire;
a source or drain region at a first side of the gate structure, the source or drain region comprising a second portion of the semiconductor sub-fin on a dielectric plug, and the source or drain region comprising an epitaxial structure on the second portion of the semiconductor sub-fin, the epitaxial structure having a second lateral width, the second lateral width substantially the same as the first lateral width;
a conductive contact structure along sidewalls of the second portion of the semiconductor sub-fin and along sidewalls of the dielectric plug; and
a pair of dielectric spacers along sidewalls of the conductive contact structure.

13. The integrated circuit structure of claim 12 , further comprising:
a second source or drain region at a second side of the gate structure, the second source or drain region comprising a third portion of the semiconductor sub-fin on a second dielectric plug; and
a second conductive contact structure along sidewalls of the third portion of the semiconductor sub-fin and along sidewalls of the second dielectric plug.

14. The integrated circuit structure of claim 12 , wherein the gate structure comprises a high-k dielectric layer, and a gate electrode comprising a metal.

15. A method of fabricating an integrated circuit structure, comprising:
forming a semiconductor nanowire above a first portion of a semiconductor sub-fin, the semiconductor sub-fin having a first lateral width;
forming a gate structure surrounding a channel portion of the semiconductor nanowire;
forming a source or drain region at a first side of the gate structure, the source or drain region comprising an epitaxial structure on a second portion of the semiconductor sub-fin, the epitaxial structure having substantially vertical sidewalls in alignment with the second portion of the semiconductor sub-fin; and
forming a conductive contact structure along sidewalls of the second portion of the semiconductor sub-fin and along the substantially vertical sidewalls of the epitaxial structure.

16. The method of claim 15 , further comprising:
forming a pair of dielectric spacers along sidewalls of the conductive contact structure.

17. The method of claim 15 , further comprising:
forming a second source or drain region at a second side of the gate structure, the second source or drain region comprising a second epitaxial structure on a third portion of the semiconductor sub-fin, the second epitaxial structure having substantially vertical sidewalls in alignment with the third portion of the semiconductor sub-fin; and
forming a second conductive contact structure along sidewalls of the third portion of the semiconductor sub-fin and along the substantially vertical sidewalls of the second epitaxial structure.

18. The method of claim 15 , further comprising:
forming a second source or drain region at a second side of the gate structure, the second source or drain region comprising a second epitaxial structure on a third portion of the semiconductor sub-fin, the second epitaxial structure having non-vertical sidewalls extending laterally beyond the third portion of the semiconductor sub-fin.

19. The method of claim 18 , further comprising:
forming a pair of dielectric spacers along the second epitaxial structure and the third portion of the semiconductor sub-fin, wherein points of the non-vertical sidewalls of the second epitaxial structure are in contact with the pair of dielectric spacers.

20. The method of claim 15 , wherein the epitaxial structure comprises a semiconductor material different than the semiconductor sub-fin and different than the semiconductor nanowire.

21. The method of claim 15 , wherein the gate structure comprises a high-k dielectric layer, and a gate electrode comprisin

Assignees

• Intel Corp

Inventors

• Mehandru Rishabh
• Ghani Tahir
• Cea Stephen
• Guha Biswajeet

Classifications

• H10W20/069

  by forming self-aligned vias or self-aligned contact plugs · CPC title

• B82Y10/00 Primary

  Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic · CPC title

• B82Y40/00

  Manufacture or treatment of nanostructures · CPC title

• H01L29/775 Primary

  Electricity · mapped topic

• H01L29/78696

  Electricity · mapped topic