Deep source and drain for transistor structures with back-side contact metallization

Patent metadata

Field	Value
Publication number	US-11688780-B2
Application number	US-201916362510-A
Country	US
Kind code	B2
Filing date	Mar 22, 2019
Priority date	Mar 22, 2019
Publication date	Jun 27, 2023
Grant date	Jun 27, 2023

Abstract

Transistor structure including deep source and/or drain semiconductor that is contacted by metallization from both a front (e.g., top) side and a back (e.g., bottom) side of transistor structure. The deep source and/or drain semiconductor may be epitaxial, following crystallinity of a channel region that may be monocrystalline A first layer of the source and/or drain semiconductor may have lower impurity doping while a second layer of the source and/or drain semiconductor may have higher impurity doping. The deep source and/or drain semiconductor may extend below the channel region and be adjacent to a sidewall of a sub-channel region such that metallization in contact with the back side of the transistor structure may pass through a thickness of the first layer of the source and/or drain semiconductor to contact the second layer of the source and/or drain semiconductor.

First claim

What is claimed is:

1. A transistor structure, comprising:
a fin comprising a channel region over a sub-channel region, the channel region comprising a first semiconductor material having a first impurity concentration;
a gate electrode adjacent to a sidewall of the channel region, and over a dielectric material that is adjacent to a sidewall of the sub-channel region;
a source region and a drain region on opposite sides of the gate electrode, wherein at least one of the source region and the drain region comprises:
a second semiconductor material that has a second impurity concentration greater than the first impurity concentration; and
a third semiconductor material between the second semiconductor material and the sidewall of both the channel region and the sub-channel region, the third semiconductor material having a third impurity concentration exceeding the first impurity concentration, but less than the second impurity concentration;

first contact metallization coupled to a first side of the source region or drain region, the first contact metallization in contact with the second semiconductor material; and
second contact metallization coupled to a second side of the source region or drain region, opposite the first side, the second contact metallization extending through a thickness of the third semiconductor material and in contact with the second semiconductor material.

2. The transistor structure of claim 1 , wherein:
the source region comprises the third semiconductor material between the sidewall of both the channel region and the sub-channel region;
and
a sidewall of the third semiconductor material that is adjacent to the sub-channel region is substantially below a sidewall of a gate spacer that is between a sidewall of the gate electrode and the source region.

3. A transistor structure, comprising:
a fin comprising a channel region over a sub-channel region, the channel region comprising a first semiconductor material having a first impurity concentration;
a gate electrode adjacent to a sidewall of the channel region, and over a dielectric material that is adjacent to a sidewall of the sub-channel region;
a source region and a drain region on opposite sides of the gate electrode, wherein at least one of the source region and the drain region comprises:
a second semiconductor material that has a second impurity concentration greater than the first impurity concentration; and
a third semiconductor material between the second semiconductor material and the sidewall of both the channel region and the sub-channel region, the third semiconductor material having a third impurity concentration exceeding the first impurity concentration, but less than the second impurity concentration;

first contact metallization coupled to a first side of the source region or drain region, the first contact metallization in contact with the second semiconductor material; and
second contact metallization coupled to a second side of the source region or drain region, opposite the first side, the second contact metallization also in contact with the second semiconductor material, wherein:
the first semiconductor material is monocrystalline and comprises predominantly silicon;
the second semiconductor material is in contact with the third semiconductor material; and
the second and third semiconductor materials have crystallinity that is epitaxial with that of the first semiconductor material.

4. The transistor structure of claim 3 , wherein:
the second semiconductor material comprises more germanium than the first semiconductor material;
the second and third semiconductor materials are both p-type; and
the second and third impurity concentrations comprise p-type impurity dopants.

5. The transistor structure of claim 3 , wherein:
the first, second, and third semiconductor materials each comprise predominantly silicon; and
the second and third semiconductor materials are both n-type, the second and third impurity concentrations comprising at least phosphorus.

6. The transistor structure of claim 3 , wherein:
the sub-channel region is a portion of a substrate layer; and
the second contact metallization extends through a thickness of the third semiconductor material that is between the second semiconductor material and the substrate layer.

7. The transistor structure of claim 6 , wherein the sub-channel region comprises predominantly silicon and has a conductivity type complementary to that of the channel region.

8. The transistor structure of claim 6 , wherein:
a sidewall of the second contact metallization is in contact with the second semiconductor material.

9. The transistor structure of claim 8 , wherein only the third semiconductor material is between the second contact metallization and the sidewall of the sub-channel region.

10. The transistor structure of claim 8 , wherein the third semiconductor material is between the second contact metallization and the sidewall of the channel region.

11. An integrated circuit (IC), comprising:
a plurality of first interconnect metallization levels;
a plurality of second interconnect metallization levels; and
an active device layer between the first and second interconnect metallization levels, the active device layer comprising a plurality of transistor structures, wherein at least one of the transistor structures further comprises:
a fin comprising a channel region over a sub-channel region, the channel region comprising a first semiconductor material having a first impurity concentration;
a gate electrode adjacent to a sidewall of the channel region, and over a dielectric material that is adjacent to a sidewall of the sub-channel region;
a source region and a drain region on opposite sides of the gate electrode, wherein at least one of the source region and the drain region comprises:
a second semiconductor material that has a second impurity concentration greater than the first impurity concentration; and
a third semiconductor material in contact with the sidewall of both the channel region and the sub-channel region, the third semiconductor material having a third impurity concentration exceeding the first impurity concentration, but less than the second impurity concentration, wherein the third semiconductor material is between the second semiconductor material and the sidewall of both the channel region and the sub-channel region;

wherein the first interconnect metallization levels comprise first contact metallization coupled to a first side of the source region or drain region, the first contact metallization in contact with the second semiconductor material; and
wherein the second interconnect metallization levels comprise second contact metallization coupled to a second side of the source region or drain region, opposite the first side, the second contact metallization extending through a portion of the third semiconductor material and in contact with the second semiconductor material.

12. The IC of claim 11 , wherein individual ones of the transistor structures are electrically isolated by a dielectric material that is between the sub-channel region and the second interconnect metallization levels.

13. A computing platform, the platform comprising:
the IC of claim 11 , and
a power supply coupled to the IC of claim 11 .

Assignees

• Intel Corp

Inventors

• Mehandru Rishabh
• Ghani Tahir
• Cea Stephen

Classifications

• H10W20/481

  on the rear surfaces of the wafers or substrates · CPC title

• H10W20/20

  Interconnections within wafers or substrates, e.g. through-silicon vias [TSV] · CPC title

• H10W20/40

  Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes · CPC title

• H10D84/834

  comprising FinFETs · CPC title

• H10D64/254

  for lateral devices wherein the source or drain electrodes extend entirely through the semiconductor bodies, e.g. via-holes for back side contacts · CPC title