Three-dimensional memory device including a silicon-germanium source contact layer and method of making the same
US-11721727-B2 · Aug 8, 2023 · US
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Baraskar Ashish patents
Baraskar Ashish is listed as an inventor on 59 patents in our database. Major assignees and classification codes are summarized below.
| Metric | Value |
|---|---|
| Inventor | Baraskar Ashish |
| Total patents | 59 |
| First publication | Mar 1, 2016 |
| Latest publication | Aug 8, 2023 |
Notable patents
Publications ranked by popularity score, then publication date.
Three-dimensional memory device with high mobility channels and nickel aluminum silicide or germanide drain contacts and method of making the same
US-11538828-B2 · Dec 27, 2022 · US
Three-dimensional memory device containing III-V compound semiconductor channel and contacts and method of making the same
US-11508748-B2 · Nov 22, 2022 · US
Three-dimensional memory device with high mobility channels and nickel aluminum silicide or germanide drain contacts and method of making the same
US-11495613-B2 · Nov 8, 2022 · US
Methods for reusing substrates during manufacture of a bonded assembly including a logic die and a memory die
US-11398451-B2 · Jul 26, 2022 · US
Three-dimensional memory device containing III-V compound semiconductor channel and contacts and method of making the same
US-11374020-B2 · Jun 28, 2022 · US
Three-dimensional memory device including a silicon-germanium source contact layer and method of making the same
US-11322509-B2 · May 3, 2022 · US
Three-dimensional memory device containing III-V compound semiconductor channel and contacts and method of making the same
US-11282857-B2 · Mar 22, 2022 · US
Three-dimensional memory device with high mobility channels and nickel aluminum silicide or germanide drain contacts and method of making the same
US-2022045088-A1 · Feb 10, 2022 · US
Three-dimensional memory device with high mobility channels and nickel aluminum silicide or germanide drain contacts and method of making the same
US-2022045087-A1 · Feb 10, 2022 · US
Recent patents
Latest publications not already listed above.
Modified verify scheme for programming a memory apparatus
US-11244734-B2 · Feb 8, 2022 · US
Three-dimensional memory device containing iii-v compound semiconductor channel and contacts and method of making the same
US-2021375910-A1 · Dec 2, 2021 · US
Three-dimensional memory device containing iii-v compound semiconductor channel and contacts and method of making the same
US-2021375908-A1 · Dec 2, 2021 · US
Three-dimensional memory device containing iii-v compound semiconductor channel and contacts and method of making the same
US-2021375909-A1 · Dec 2, 2021 · US
Three-dimensional memory device containing plural work function word lines and methods of forming the same
US-11101288-B2 · Aug 24, 2021 · US
Three-dimensional memory device containing plural work function word lines and methods of forming the same
US-11063063-B2 · Jul 13, 2021 · US
Modified verify scheme for programming a memory apparatus
US-2021202022-A1 · Jul 1, 2021 · US
Three-dimensional memory device containing plural work function word lines and methods of forming the same
US-2021183883-A1 · Jun 17, 2021 · US
Three-dimensional memory device containing plural work function word lines and methods of forming the same
US-2021183882-A1 · Jun 17, 2021 · US
Multi-pass programming process for memory device which omits verify test in first program pass
US-11037640-B2 · Jun 15, 2021 · US
Memory device with compensation for program speed variations due to block oxide thinning
US-11024387-B2 · Jun 1, 2021 · US
Reprogramming memory cells to tighten threshold voltage distributions and improve data retention
US-10964402-B1 · Mar 30, 2021 · US
Methods for reusing substrates during manufacture of a bonded assembly including a logic die and a memory die
US-2021082865-A1 · Mar 18, 2021 · US
Memory device with compensation for program speed variations due to block oxide thinning
US-2021082515-A1 · Mar 18, 2021 · US
Memory device with compensation for erase speed variations due to blocking oxide layer thinning
US-10923197-B2 · Feb 16, 2021 · US
Memory device with compensation for program speed variations due to block oxide thinning
US-10878914-B2 · Dec 29, 2020 · US
Three-dimensional memory device including a silicon-germanium source contact layer and method of making the same
US-2020388626-A1 · Dec 10, 2020 · US
Three-dimensional memory device including a silicon-germanium source contact layer and method of making the same
US-2020388688-A1 · Dec 10, 2020 · US
Memory device with compensation for erase speed variations due to blocking oxide layer thinning
US-2020335168-A1 · Oct 22, 2020 · US
Multi-pass programming process for memory device which omits verify test in first program pass
US-10811109-B2 · Oct 20, 2020 · US
Major assignees
Companies most often associated with this inventor's publications.
| Assignee | Patents |
|---|---|
| Sandisk Technologies Llc | 51 |
| Globalfoundries Inc | 7 |
| Sandisk Technologies Llc | 1 |
Top CPC classifications
Most common classification codes across this inventor's patents.
| CPC | Patents |
|---|---|
| H10B43/27 | 45 |
| H10B43/10 | 41 |
| H01L27/11582 | 37 |
| H10B43/35 | 36 |
| H01L27/1157 | 33 |