Three-dimensional memory device containing III-V compound semiconductor channel and contacts and method of making the same

Patent metadata

Field	Value
Publication number	US-11508748-B2
Application number	US-202016887818-A
Country	US
Kind code	B2
Filing date	May 29, 2020
Priority date	May 29, 2020
Publication date	Nov 22, 2022
Grant date	Nov 22, 2022

Abstract

A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers, and a memory stack structure vertically extending through the alternating stack. The memory stack structure includes a vertical semiconductor channel and a memory film. The vertical semiconductor channel can include a III-V compound semiconductor channel material. A III-V compound substrate semiconductor layer or a III-V compound semiconductor source region can be used to provide low-resistance electrical connection to a bottom end of the vertical semiconductor channel, and a drain region including a graded III-V compound semiconductor material can be used to provide low-resistance electrical connection to a top end of the vertical semiconductor channel.

First claim

What is claimed is:

1. A three-dimensional memory device, comprising:
a source-level contact layer overlying a substrate and comprising a III-V compound semiconductor source region;
at least one alternating stack of insulating layers and electrically conductive layers located over the source-level contact layer;
a memory opening vertically extending through the at least one alternating stack; and
a memory opening fill structure located in the memory opening and comprising a vertical semiconductor channel comprising a III-V compound semiconductor channel material in contact with an inner sidewall of the III-V compound semiconductor source region, and a memory film located adjacent to the vertical semiconductor channel,
wherein the source-level contact layer further comprises an annular metal germanosilicide portion contacting and laterally surrounding the III-V compound semiconductor source region.

2. The three-dimensional memory device of claim 1 , wherein the source-level contact layer further comprises a source-level metallic layer contacting an outer sidewall of the annular metal germanosilicide portion.

3. The three-dimensional memory device of claim 2 , wherein a bottom surface of a bottommost one of the insulating layers contacts an annular top surface of the III-V compound semiconductor source region, the annular metal germanosilicide portion, and the source-level metallic layer.

4. The three-dimensional memory device of claim 2 , wherein the electrically conductive layers have a same material composition as the source-level metallic layer.

5. The three-dimensional memory device of claim 2 , wherein the annular metal germanosilicide portion comprises nickel germanosilicide.

6. The three-dimensional memory device of claim 1 , wherein the memory film comprises:
a tunneling dielectric layer contacting the vertical semiconductor channel;
a charge storage layer in contact with the tunneling dielectric layer; and
a blocking dielectric layer located between the charge storage layer and the electrically conductive layers.

7. A three-dimensional memory device, comprising:
a source-level contact layer overlying a substrate and comprising a III-V compound semiconductor source region;
at least one alternating stack of insulating layers and electrically conductive layers located over the source-level contact layer;
a memory opening vertically extending through the at least one alternating stack; and
a memory opening fill structure located in the memory opening and comprising a vertical semiconductor channel comprising a III-V compound semiconductor channel material in contact with an inner sidewall of the III-V compound semiconductor source region, and a memory film located adjacent to the vertical semiconductor channel,
wherein:
the III-V compound semiconductor channel material comprises gallium arsenide or indium gallium arsenide having a fixed band gap that is uniform throughout the vertical semiconductor channel; and
the III-V compound semiconductor source region comprises indium gallium arsenide that has a variable band gap that is smaller than the fixed band gap of the III-V compound semiconductor channel material, and that decreases within the III-V compound semiconductor source region with a lateral distance from a cylindrical interface with the vertical semiconductor channel.

8. The three-dimensional memory device of claim 7 , wherein the III-V compound semiconductor source region comprises a doped indium gallium arsenide layer having a graded indium concentration which increases within the III-V compound semiconductor source region with a distance from an interface with the vertical semiconductor channel.

9. A three-dimensional memory device, comprising:
a source-level contact layer overlying a substrate and comprising a III-V compound semiconductor source region;
at least one alternating stack of insulating layers and electrically conductive layers located over the source-level contact layer;
a memory opening vertically extending through the at least one alternating stack; and
a memory opening fill structure located in the memory opening and comprising a vertical semiconductor channel comprising a III-V compound semiconductor channel material in contact with an inner sidewall of the III-V compound semiconductor source region, and a memory film located adjacent to the vertical semiconductor channel,
wherein:
the III-V compound semiconductor source region comprises a stack of cylindrical III-V compound material layers having different material compositions; and
the cylindrical III-V compound material layers have different band gaps that decrease with a lateral distance from a cylindrical interface with the vertical semiconductor channel.

10. The three-dimensional memory device of claim 9 , wherein:
the vertical semiconductor channel comprises a gallium arsenide material; and
the stack of cylindrical III-V compound material layers comprises at least one indium gallium arsenide layer.

11. The three-dimensional memory device of claim 9 , wherein:
the vertical semiconductor channel has a doping of a first conductivity type; and
the III-V compound semiconductor source region has a doping of a second conductivity type that is an opposite of the first conductivity type.

12. The three-dimensional memory device of claim 11 , further comprising a drain region including a graded III-V compound semiconductor material having a doping of a second conductivity type that is an opposite of the first conductivity type.

13. The three-dimensional memory device of claim 12 , wherein the drain region has a compositional gradient therein such that a variable band gap within the drain region decreases with a distance from an interface with the vertical semiconductor channel.

Assignees

• Sandisk Technologies Llc

Inventors

• Baraskar Ashish
• Rabkin Peter
• Makala Raghuveer S

Classifications

• H10W20/42

  Vias, e.g. via plugs · CPC title

• H01L27/11543

  Electricity · mapped topic

• H01L27/11524

  Electricity · mapped topic

• H01L27/11582 Primary

  Electricity · mapped topic

• H01L27/11519

  Electricity · mapped topic