Methods for reusing substrates during manufacture of a bonded assembly including a logic die and a memory die

Patent metadata

Field	Value
Publication number	US-11398451-B2
Application number	US-202017106831-A
Country	US
Kind code	B2
Filing date	Nov 30, 2020
Priority date	Mar 1, 2019
Publication date	Jul 26, 2022
Grant date	Jul 26, 2022

Abstract

A semiconductor structure includes a memory die bonded to a support die. The memory die includes an alternating stack of insulating layers and electrically conductive layers located over a first single crystalline semiconductor layer, and memory stack structures extending through the alternating stack and containing respective memory film and a respective vertical semiconductor channel including a single crystalline channel semiconductor material. The support die includes a peripheral circuitry. Substrates employed to provide the memory die and the support die can be reused by replacing one of the substrates with an alternative low-cost substrate that provides structural support to the bonded assembly.

First claim

What is claimed is:

1. A method of forming a bonded semiconductor structure, comprising:
providing a first semiconductor structure comprising a vertical stack including a first substrate, a first sacrificial layer, and a first semiconductor device assembly including first metal interconnect structures and first metal bonding pads embedded in first dielectric material layers;
providing a second semiconductor structure comprising a vertical stack including a second substrate, and a second semiconductor device assembly including second metal interconnect structures and second metal bonding pads embedded in second dielectric material layers;
bonding the second metal bonding pads with the first metal bonding pads;
detaching the first substrate from an assembly of the second semiconductor structure and the first semiconductor device assembly by removing the first sacrificial layer; and
attaching a replacement substrate to the first semiconductor device assembly.

2. The method of claim 1 , wherein the second semiconductor structure further comprises a second sacrificial layer.

3. The method of claim 2 , further comprising detaching the second substrate from an assembly of the replacement substrate, the first semiconductor device assembly, and the second semiconductor device assembly by removing the second sacrificial layer.

4. The method of claim 3 , wherein:
the first sacrificial layer is removed by performing an isotropic etch process that removes a material of the first sacrificial layer selective to a material of the first substrate and a material of a surface portion of the first semiconductor device assembly in contact with the first sacrificial layer; and
the second sacrificial layer is removed by performing an isotropic etch process that removes a material of the second sacrificial layer selective to a material of the second substrate and a material of a surface portion of the second semiconductor device assembly in contact with the second sacrificial layer.

5. The method of claim 4 , wherein the second sacrificial layer comprises a material selected from undoped silicate glass, a doped silicate glass, organosilicate glass, and a silicon-germanium alloy.

6. The method of claim 3 , wherein:
the first substrate comprises a first single crystalline or polycrystalline semiconductor substrate; and
the second substrate comprises a second single crystalline semiconductor substrate.

7. The method of claim 6 , wherein the replacement substrate comprises a polycrystalline semiconductor substrate, a glass substrate, a metallic substrate, or a polymer substrate.

8. The method of claim 3 , wherein the first semiconductor device assembly comprises a three-dimensional memory device including an alternating stack of insulating layers and electrically conductive layers and memory stack structures vertically extending through the alternating stack, wherein each of the memory stack structures comprises a respective vertical semiconductor channel and a respective memory film.

9. The method of claim 8 , wherein the second semiconductor device assembly comprises a peripheral circuit configured to control operation of the three-dimensional memory device by transmitting control signals through bonded pairs of the first metal bonding pads and the second metal bonding pads.

10. The method of claim 9 , wherein the second semiconductor device assembly comprises a single crystalline semiconductor layer in contact with the second sacrificial layer.

11. The method of claim 10 , further comprising:
forming a first silicon oxide layer on a surface of a single crystalline semiconductor substrate;
forming a hydrogen implantation layer within the single crystalline semiconductor substrate by implanting hydrogen atoms;
forming a second silicon oxide layer on a surface of the second substrate;
bonding the first silicon oxide layer with the second silicon oxide layer to form the second sacrificial layer; and
cleaving the single crystalline semiconductor substrate along the hydrogen implantation layer, wherein a portion of the single crystalline semiconductor substrate that is attached to the sacrificial layer comprises the single crystalline semiconductor layer.

12. The method of claim 11 , wherein the first semiconductor device assembly comprises a polycrystalline semiconductor layer in contact with the first sacrificial layer.

13. The method of claim 12 , further comprising:
forming the first sacrificial layer on a surface of the first substrate; and
forming the polycrystalline semiconductor layer on the first sacrificial layer.

14. The method of claim 3 , further comprising:
forming a first dielectric passivation layer on sidewalls of the first semiconductor structure, wherein a surface of the first sacrificial layer is not covered by the first dielectric passivation layer; and
forming a second dielectric passivation layer on sidewalls of the second semiconductor structure, wherein all surfaces of the second sacrificial layer contact a respective one of the second substrate, the second semiconductor device assembly, and the second dielectric passivation layer.

15. The method of claim 14 , wherein the first sacrificial layer is removed by providing an isotropic etchant that etches a material of the first sacrificial layer selective to a material of the first dielectric passivation layer and the second dielectric passivation layer.

16. The method of claim 15 , further comprising:
removing horizontal portions of the first dielectric passivation layer by performing an anisotropic etch process; and
removing a horizontal portion of the second dielectric passivation layer from above the second semiconductor device assembly by performing a chemical mechanical planarization process.

17. The method of claim 16 , further comprising:
anisotropically etching horizontal portions of the second dielectric passivation layer after attaching the replacement substrate to the first semiconductor device assembly, wherein a surface of the second sacrificial layer is physically exposed; and
removing the second sacrificial layer by applying an isotropic etchant that etches a material of the second sacrificial layer selective to materials of the first dielectric passivation layer and the second dielectric passivation layer.

18. The method of claim 1 , further comprising attaching a third semiconductor structure to the second semiconductor structure, wherein:
one of the first semiconductor structure, the second semiconductor structure, and the third semiconductor structure comprises a memory die including a three-dimensional array of memory elements; and
another of the first semiconductor structure, the second semiconductor structure, and the third semiconductor structure comprises a support die including a peripheral circuit for controlling operation of the three-dimensional array of memory elements.

19. The method of claim 1 , wherein:
the first semiconductor structure comprises a plurality of first semiconductor dies located on the first substrate; and
the second semiconductor structure comprises a plurality of second semiconductor dies located on the second substrate.

20. A semiconductor structure, comprising:
a first semiconductor die comprising a first semiconductor device assembly including first metal interconnect structures and first metal bonding pads embedded in first dielectric material layers;
a second semiconductor die comprising a second semiconductor device assembly including second metal interconnect structures and second me

Assignees

• Sandisk Technologies Llc

Inventors

• Baraskar Ashish
• Makala Raghuveer S
• Rabkin Peter

Classifications

• H10P72/744

  Details of chemical or physical process used for separating the auxiliary support from a device or a wafer · CPC title

• H10W10/181

  Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers · CPC title

• H10P90/1916

  with separation or delamination along an ion implanted layer, e.g. Smart-cut · CPC title

• H10P72/74

  using temporarily an auxiliary support · CPC title

• H10W90/792

  between multiple chips · CPC title