Three-dimensional memory device containing plural work function word lines and methods of forming the same

US11063063B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-11063063-B2
Application numberUS-201916710481-A
CountryUS
Kind codeB2
Filing dateDec 11, 2019
Priority dateDec 11, 2019
Publication dateJul 13, 2021
Grant dateJul 13, 2021

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, memory openings vertically extending through the alternating stack, and memory stack structures extending through the alternating stack. Each of the memory stack structures contains a memory film and a vertical semiconductor channel. At least one of the electrically conductive layers contains a first conductive material portion having a respective inner sidewall that contacts a respective one of the memory films at a vertical interface, and a second conductive material portion that has a different composition from the first conductive material portion, and contacting the first electrically conductive material portion. The first conductive material portion has a lower work function than the second conductive material portion.

First claim

Opening claim text (preview).

What is claimed is: 1. A three-dimensional memory device comprising: an alternating stack of insulating layers and electrically conductive layers located over a substrate; memory openings vertically extending through the alternating stack; and memory stack structures extending through the alternating stack, wherein: each of the memory stack structures comprises a memory film and a vertical semiconductor channel; and at least one of the electrically conductive layers comprises: a first conductive material portion having a respective inner sidewall that contacts a respective one of the memory films at a vertical interface; and a second conductive material portion that has a different composition from the first conductive material portion, and contacting the first electrically conductive material portion, a bottom surface of a first one of the insulating layers and a top surface of a second one of the insulating layers, wherein the first conductive material portion has a lower work function than the second conductive material portion. 2. The three-dimensional memory device of claim 1 , wherein the second conductive material portion laterally surrounds the first conductive material portion. 3. The three-dimensional memory device of claim 1 , wherein the first conductive material portion has a respective upper annular surface that contacts the bottom surface of the first one of the insulating layers, and a respective lower annular surface that contacts the top surface of the second one of the insulating layers. 4. The three-dimensional memory device of claim 1 , wherein the inner sidewall of the first conductive material portion is vertically coincident with interface between the memory film and the insulating layers. 5. The three-dimensional memory device of claim 1 , wherein the first conductive material portion has a respective outer sidewall that is laterally offset from the respective inner sidewall by a thickness of the first conductive material portion. 6. The three-dimensional memory device of claim 1 , wherein the thickness of the first conductive material portion is in a range from 0.5 nm to 15 nm. 7. The three-dimensional memory device of claim 1 , wherein: the first conductive material portion comprises ruthenium; and the second conductive material portion comprises a metallic nitride, tungsten, or cobalt. 8. The three-dimensional memory device of claim 7 , wherein the second conductive material portion comprises titanium nitride. 9. The three-dimensional memory device of claim 1 , wherein: the first conductive material portion comprises n-type polysilicon; and the second conductive material portion comprises a metallic nitride, tungsten, or cobalt. 10. The three-dimensional memory device of claim 9 , wherein the second conductive material portion comprises titanium nitride. 11. The three-dimensional memory device of claim 10 , wherein: the first conductive material portion has a tubular configuration; an entirety of an outer cylindrical sidewall of the first conductive material portion is in contact with an inner sidewall of the second conductive material portion; and the second conductive material portion comprises: tubular portion that laterally surrounds the first conductive material portion; an upper horizontally extending portion adjoined to an upper end of the tubular portion; and a lower horizontally extending portion adjoined to a lower end the tubular portion. 12. The three-dimensional memory device of claim 11 , wherein each of the tubular portion, the upper horizontally extending portion, and the lower horizontally extending portion contacts a tungsten portion. 13. The three-dimensional memory device of claim 9 , wherein the second conductive material portion comprises cobalt. 14. The three-dimensional memory device of claim 13 , further comprising a backside trench fill structure contacting sidewalls of the alternating stack, wherein the second conductive material portion does not contact the backside trench fill structure, and is laterally spaced from the backside trench fill structure by a third conductive material portion having a composition that is different from the second conductive material portion. 15. The three-dimensional memory device of claim 14 , wherein the third conductive material portion comprises at least one of tungsten or conductive metallic nitride.

Assignees

Inventors

Classifications

  • by chemical means · CPC title

  • Semiconductor materials, e.g. polysilicon · CPC title

  • the principal metal being a refractory metal · CPC title

  • the principal metal being a noble metal, e.g. gold · CPC title

  • Layouts of interconnections · CPC title

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What does patent US11063063B2 cover?
A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, memory openings vertically extending through the alternating stack, and memory stack structures extending through the alternating stack. Each of the memory stack structures contains a memory film and a vertical semiconductor channel. At least one of t…
Who is the assignee on this patent?
Sandisk Technologies Llc
What technology area does this patent fall under?
Primary CPC classification H10D64/037. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Jul 13 2021 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 12 related publications on this page (citations in our corpus or others sharing the same primary CPC).