Three-dimensional memory device with high mobility channels and nickel aluminum silicide or germanide drain contacts and method of making the same

Patent metadata

Field	Value
Publication number	US-11538828-B2
Application number	US-202016984920-A
Country	US
Kind code	B2
Filing date	Aug 4, 2020
Priority date	Aug 4, 2020
Publication date	Dec 27, 2022
Grant date	Dec 27, 2022

Abstract

A memory device can include a strained single-crystalline silicon layer and an alternating stack of insulating layers and electrically conductive layers located over the strained single-crystalline silicon layer. A memory opening fill structure extending through the alternating stack may include an epitaxial silicon-containing pedestal channel portion, and a vertical semiconductor channel, and a vertical stack of memory elements located adjacent to the vertical semiconductor channel. Additionally or alternatively, a drain region can include a semiconductor drain portion and a nickel-aluminum-semiconductor alloy drain portion.

First claim

What is claimed is:

1. A memory device comprising:
a strained single-crystalline silicon layer;
an alternating stack of insulating layers and electrically conductive layers located over the strained single-crystalline silicon layer;
a memory opening vertically extending through the alternating stack; and
a memory opening fill structure located in the memory opening and comprising an epitaxial silicon-containing pedestal channel portion in epitaxial alignment with the strained single-crystalline silicon layer, a vertical semiconductor channel, a vertical stack of memory elements located adjacent to the vertical semiconductor channel at levels of the electrically conductive layers, and a drain region;
wherein:
the single-crystalline silicon-germanium compound semiconductor layer has a first thickness;
the strained single-crystalline silicon layer has a second thickness; and
a ratio of the second thickness to the first thickness is in a range from 1:1000 to 1:10.

2. The memory device of claim 1 , further comprising a single-crystalline silicon-germanium compound semiconductor layer, wherein the strained single-crystalline silicon layer is located on and in epitaxial alignment with the single-crystalline silicon-germanium compound semiconductor layer.

3. The memory device of claim 2 , wherein:
the strained single-crystalline silicon layer and the epitaxial silicon-containing pedestal channel portion have a doping of a first conductivity type; and
a source region having a doping of a second conductivity type opposite to the first conductivity type is in contact with the strained single-crystalline silicon layer and is located outside the memory opening.

4. The memory device of claim 3 , wherein the source region comprises:
a lower source portion comprising a doped single-crystalline silicon-germanium compound semiconductor material having a doping of the second conductivity type; and
an upper source portion comprising a doped single-crystalline strained silicon material and having a doping of the second conductivity type.

5. The memory device of claim 3 , wherein:
the single-crystalline silicon-germanium compound semiconductor layer has a doping of the first conductivity type or is intrinsic;
the vertical semiconductor channel is intrinsic or has a doping of the first conductivity type; and
the drain region comprises a semiconductor material having a doping of the second conductivity type.

6. The memory device of claim 2 , wherein:
the single-crystalline silicon-germanium compound semiconductor layer comprises a compositionally graded single-crystalline silicon-germanium compound semiconductor material in which an atomic percentage of germanium increases monotonically with a vertical distance from the substrate single-crystalline silicon layer;
an atomic percentage of germanium in the single-crystalline silicon-germanium compound semiconductor layer is in a range from 10% to 80%; and
the strained single-crystalline silicon layer is free of germanium or includes germanium atoms at an atomic percentage less than 0.1%.

7. The memory device of claim 2 , wherein the single-crystalline silicon-germanium compound semiconductor layer is formed on a single-crystalline silicon substrate.

8. The memory device of claim 1 , wherein:
the single-crystalline silicon-germanium compound semiconductor layer has a variable in-plane lattice constant that increases monotonically with a vertical distance from the substrate single-crystalline silicon layer; and
a dislocation density decreases with the vertical distance from the substrate single-crystalline silicon layer within an upper region of the single-crystalline silicon-germanium compound semiconductor layer.

9. The memory device of claim 1 , wherein the drain region comprises:
a semiconductor drain portion including a doped silicon-containing semiconductor material and contacting an end portion of the vertical semiconductor channel; and
a nickel-aluminum-semiconductor alloy drain portion comprising silicon.

10. The memory device of claim 9 , further comprising a metallic drain electrode comprising an elemental metal or a conductive metallic nitride material in contact with a top surface of the nickel-aluminum-semiconductor alloy drain portion.

11. The memory device of claim 1 , wherein the epitaxial silicon-containing pedestal channel portion comprises single-crystalline silicon or single-crystalline silicon-germanium compound semiconductor layer.

12. The memory device of claim 1 , wherein:
the memory opening fill structure comprises a memory film including a layer stack containing at least a charge storage layer and a tunneling dielectric layer; and
the vertical stack of memory elements comprises portions of the charge storage layer located at levels of the electrically conductive layers.

13. A memory device comprising:
a strained single-crystalline silicon layer;
an alternating stack of insulating layers and electrically conductive layers located over the strained single-crystalline silicon layer;
a memory opening vertically extending through the alternating stack;
a memory opening fill structure located in the memory opening and comprising an epitaxial silicon-containing pedestal channel portion in epitaxial alignment with the strained single-crystalline silicon layer, a vertical semiconductor channel, a vertical stack of memory elements located adjacent to the vertical semiconductor channel at levels of the electrically conductive layers, and a drain region; and
a single-crystalline silicon-germanium compound semiconductor layer,
wherein:
the strained single-crystalline silicon layer is located on and in epitaxial alignment with the single-crystalline silicon-germanium compound semiconductor layer;
the strained single-crystalline silicon layer and the epitaxial silicon-containing pedestal channel portion have a doping of a first conductivity type;
a source region having a doping of a second conductivity type opposite to the first conductivity type is in contact with the strained single-crystalline silicon layer and is located outside the memory opening; and
the source region comprises:
a lower source portion comprising a doped single-crystalline silicon-germanium compound semiconductor material having a doping of the second conductivity type; and
an upper source portion comprising a doped single-crystalline strained silicon material and having a doping of the second conductivity type.

14. A memory device comprising:
a strained single-crystalline silicon layer;
an alternating stack of insulating layers and electrically conductive layers located over the strained single-crystalline silicon layer;
a memory opening vertically extending through the alternating stack; and
a memory opening fill structure located in the memory opening and comprising an epitaxial silicon-containing pedestal channel portion in epitaxial alignment with the strained single-crystalline silicon layer, a vertical semiconductor channel, a vertical stack of memory elements located adjacent to the vertical semiconductor channel at levels of the electrically conductive layers, and a drain region;
wherein:
the single-crystalline silicon-germanium compound semiconductor layer has a variable in-plane lattice constant that increases monotonically with a vertical distance from the substrate single-crystalline silicon layer; and
a dislocation density decreases with the vertical distance from the substrate single-crystalline silicon layer within an upper region of the single-crystalline silicon-germanium compound semiconductor layer.

15. A memory device comprising

Assignees

• Sandisk Technologies Llc

Inventors

• Baraskar Ashish
• Makala Raghuveer S
• Rabkin Peter

Classifications

• H01L27/11524

  Electricity · mapped topic

• H01L27/11565

  Electricity · mapped topic

• H01L27/11519

  Electricity · mapped topic

• H01L27/1157

  Electricity · mapped topic

• H01L29/41725

  Electricity · mapped topic