Three-dimensional memory device containing plural work function word lines and methods of forming the same

Patent metadata

Field	Value
Publication number	US-11101288-B2
Application number	US-201916710572-A
Country	US
Kind code	B2
Filing date	Dec 11, 2019
Priority date	Dec 11, 2019
Publication date	Aug 24, 2021
Grant date	Aug 24, 2021

Abstract

A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, memory openings vertically extending through the alternating stack, and memory stack structures extending through the alternating stack. Each of the memory stack structures contains a memory film and a vertical semiconductor channel. At least one of the electrically conductive layers contains a first conductive material portion having a respective inner sidewall that contacts a respective one of the memory films at a vertical interface, and a second conductive material portion that has a different composition from the first conductive material portion, and contacting the first electrically conductive material portion. The first conductive material portion has a lower work function than the second conductive material portion.

First claim

What is claimed is:

1. A three-dimensional memory device comprising:
an alternating stack of insulating layers and electrically conductive layers located over a substrate;
memory openings vertically extending through the alternating stack; and
memory stack structures extending through the alternating stack,

wherein:
each of the memory stack structures comprises a memory film and a vertical semiconductor channel; and
at least one of the electrically conductive layers comprises a layer stack including, from bottom to top, a lower conductive liner, a conductive material layer, and an upper conductive liner, wherein each of the lower conductive liner, the conductive material layer, and the upper conductive liner contacts the memory films, wherein the conductive material layer has a lower work function than the lower and upper conductive liners;
wherein:
the conductive material layer has a first conductive material composition, and the lower conductive liner and the upper conductive liner have a second conductive material composition that is different from the first conductive material composition;
the first conductive material composition comprises TiN, TaN, or WN; and
the second conductive material composition comprises a p-type doped semiconductor material.

2. The three-dimensional memory device of claim 1 , wherein a blocking dielectric is not located between the insulating layers and the electrically conductive layers.

3. The three-dimensional memory device of claim 1 , wherein the first conductive material composition comprises the TiN.

4. The three-dimensional memory device of claim 1 , wherein interfaces between the conductive material layer and the memory films are vertically coincident with interfaces between the memory films and the insulating layers.

5. The three-dimensional memory device of claim 1 , wherein:
the lower conductive liner and the upper conductive liner have a respective thickness that is in a range from 2% to 20% of a thickness of the conductive material layer;
the lower conductive liner has a thickness in a range from 0.5 nm to 5 nm;
the conductive material layer has a thickness in a range from 15 nm to 40 nm; and
the upper conductive liner has a thickness in a range from 0.5 nm to 5 nm.

6. The three-dimensional memory device of claim 1 , wherein the conductive material layer comprises:
tubular portions that laterally surround a respective one of the memory films;
an upper horizontally extending portion adjoined to an upper end of each of the tubular portions; and
a lower horizontally extending portion adjoined to a lower end of each of the tubular portions.

7. The three-dimensional memory device of claim 6 , wherein the layer stack further comprises a conductive fill material layer embedded in the conductive material layer and laterally spaced from the memory films by the tubular portion of the conductive material layer.

8. The three-dimensional memory device of claim 1 , wherein each of the memory films comprises a stack including, from outside to inside, a blocking dielectric layer, a charge storage layer, and a tunneling dielectric layer that contacts a respective one of the vertical semiconductor channels.

9. The three-dimensional memory device of claim 8 , wherein the charge storage layer continuously extends vertically through multiple electrically conductive layers within the alternating stack.

10. The three-dimensional memory device of claim 1 , further comprising a backside trench fill structure contacting sidewalls of the alternating stack, wherein each of the lower conductive liners, the conductive material layers, and the upper conductive liners of the electrically conductive layers contacts the backside trench fill structure.

11. The three-dimensional memory device of claim 1 , further comprising:
a staircase region in which the electrically conductive layers in the alternating stack have stepped surfaces; and
word line contact via structures that contact a respective one of the electrically conductive layers.

12. A method of forming a three-dimensional memory device, comprising:
forming a vertical repetition of a unit layer stack including an insulating layer, a lower conductive liner, a sacrificial material layer, and an upper conductive liner over a substrate;
forming memory openings through the vertical repetition;
forming memory opening fill structures in the memory openings, wherein each of the memory opening fill structures comprises a memory film and a vertical semiconductor channel;
forming backside recesses by removing the sacrificial material layers selective to the insulating layers, the lower conductive liners, and the upper conductive liners; and
forming electrically conductive layers within the backside recesses, wherein each of the electrically conductive layers comprises a respective one of the lower conductive liners, a respective one of the upper conductive liners, and a respective conductive material layer located between the respective one of the lower conductive liners and the respective one of the upper conductive liners, wherein the conductive material layer has a lower work function than the lower and upper conductive liners.

13. The method of claim 12 , wherein the conductive material layers have a first conductive material composition, and the lower conductive liners and the upper conductive liners have a second conductive material composition that is different from the first conductive material composition.

14. The method of claim 13 , wherein a blocking dielectric is not located in the backside recesses.

15. The method of claim 13 , wherein:
the first conductive material composition comprises TiN, TaN, or WN; and
the second conductive material composition comprises a p-type doped polysilicon.

16. The method of claim 12 , wherein each of the memory films is formed by sequentially depositing a blocking dielectric layer, a charge storage layer, and a tunneling dielectric layer, and by removing portions of the blocking dielectric layer, the charge storage layer, and the tunneling dielectric layer from outside the memory openings.

17. The method of claim 12 , further comprising forming a backside trench through the vertical repetition of the unit layer stack, wherein the backside recesses are formed by introducing an isotropic etchant that etches the sacrificial material layers selective to the insulating layers, the lower conductive liners, and the upper conductive liners into the backside trench.

18. The method of claim 12 , further comprising:
forming stepped surfaces by patterning the vertical repetition of the unit layer stack in a staircase region; and
forming contact via structures on a respective one of the electrically conductive layers in the staircase region.

19. A three-dimensional memory device comprising:
an alternating stack of insulating layers and electrically conductive layers located over a substrate;
memory openings vertically extending through the alternating stack; and
memory stack structures extending through the alternating stack,

wherein:
each of the memory stack structures comprises a memory film and a vertical semiconductor channel; and
at least one of the electrically conductive layers comprises a layer stack including, from bottom to top, a lower conductive liner, a conductive material layer, and an upper conductive liner, wherein each of the lower conductive liner, the conductive material layer, and the upper conductive liner contacts the memory films, wherein the conductive material layer

Assignees

• Sandisk Technologies Llc

Inventors

• Zhang Yanli
• Moon Dong-Il
• Makala Raghuveer S
• Zhang Peng
• Zhao Wei
• Baraskar Ashish

Classifications

• H10W20/4451

  Semiconductor materials, e.g. polysilicon · CPC title

• H10W20/425

  Barrier, adhesion or liner layers · CPC title

• H10W20/081

  by forming openings in the dielectric parts · CPC title

• H10W20/056

  by filling conductive material into holes, grooves or trenches · CPC title

• H10W20/43

  Layouts of interconnections · CPC title