Multi-pass programming process for memory device which omits verify test in first program pass

Patent metadata

Field	Value
Publication number	US-11037640-B2
Application number	US-202016900015-A
Country	US
Kind code	B2
Filing date	Jun 12, 2020
Priority date	Dec 27, 2018
Publication date	Jun 15, 2021
Grant date	Jun 15, 2021

Abstract

Techniques are provided to reduce neighbor word line interference and charge loss in a multi-pass program operation. In one implementation, the first pass of a multi-pass program operation uses one or more program pulses without performing associated verify tests. The memory cells may be programmed to different intermediate threshold voltage (Vth) distributions in the first program pass. Different bit line voltages can be used to obtain the different intermediate Vth distributions when the single program pulse is applied. In other cases, multiple program pulses are applied without performing verify tests. The intermediate Vth distributions can be provided for the memory cells assigned to the higher data states but not the lower data states, or for memory cells assigned to both the higher and lower data states.

First claim

We claim:

1. An apparatus, comprising:
a set of memory cells connected to a word line, each memory cell is in a respective NAND string, the respective NAND strings are connected to a set of bit lines; and
a control circuit, the control circuit, to perform a first program pass of a program operation, is configured to
apply a first set of program pulses to the word line without performing verify tests for the memory cells, while applying a program-inhibit voltage to respective bit lines for progressively larger portions of the memory cells and applying a program-enable voltage to respective bit lines for progressively smaller portions of the memory cells over successive program pulses of the first set of program pulses; and
to perform a second program pass of the program operation, the control circuit is configured to apply a second set of program pulses to the word line and to perform verify tests after each program pulse of the second set of program pulses.

2. The apparatus of claim 1 , wherein:
the set of memory cells comprises memory cells programmed to a plurality of intermediate threshold voltage distributions in the first program pass; and
a number of program pulses in the first set of program pulses is equal to a number of intermediate threshold voltage distributions in the plurality of intermediate threshold voltage distributions.

3. The apparatus of claim 1 , wherein:
the set of memory cells comprises memory cells programmed to a plurality of intermediate threshold voltage distributions in the first program pass; and
the plurality of intermediate threshold voltage distributions are mapped to a plurality of final threshold voltage distributions in the second program pass on a one-to-one basis where each different intermediate threshold voltage distribution is mapped to a different final threshold voltage distribution.

4. The apparatus of claim 1 , wherein:
the set of memory cells comprises memory cells programmed to a plurality of intermediate threshold voltage distributions in the first program pass; and
the intermediate threshold voltage distributions are mapped to final threshold voltage distributions in the second program pass on a one-to-many basis where each different intermediate threshold voltage distribution is mapped to multiple final threshold voltage distributions.

5. The apparatus of claim 1 , wherein:
the set of memory cells comprises memory cells which are configured to be assigned to a plurality of programmed data states and which are programmed to a plurality of intermediate threshold voltage distributions in the first program pass; and
each intermediate threshold voltage distribution comprises threshold voltages of memory cells assigned to a single data state among the plurality of programmed data states.

6. The apparatus of claim 5 , wherein:
for each intermediate threshold voltage distribution, memory cells assigned to the single data state are programmed to a Vth distribution of the single data state in the second program pass.

7. The apparatus of claim 1 , wherein:
the set of memory cells comprises memory cells which are configured to be assigned to a plurality of programmed data states and which are programmed to a plurality of intermediate threshold voltage distributions in the first program pass; and
each intermediate threshold voltage distribution comprises threshold voltages of memory cells assigned to multiple programmed data states among the plurality of programmed data states.

8. The apparatus of claim 7 , wherein:
for each intermediate threshold voltage distribution, memory cells assigned to the multiple programmed data states are programmed to a Vth distribution of their programmed data state in the second program pass.

9. The apparatus of claim 1 , wherein:
the set of memory cells comprises memory cells which are configured to be assigned to a plurality of programmed data states and which are programmed to a plurality of intermediate threshold voltage distributions in the first program pass, and memory cells which are inhibited from programming and remain in an erased data state in the first program pass;
the memory cells inhibited from programming in the first program pass comprise memory cells configured to be assigned to the erased data state and memory cells configured to be assigned to at least one programmed data state; and
the at least one programmed data state has a verify voltage which is lower than verify voltages of the plurality of programmed data states.

10. The apparatus of claim 1 , wherein:
the set of memory cells comprises memory cells which are configured to be assigned to an upper half of a set of data states and which are programmed to a plurality of intermediate threshold voltage distributions in the first program pass, and memory cells which are configured to be assigned to a lower half of the set of data states and which are inhibited from programming and remain in an erased data state in the first program pass;
verify voltages of the lower half of the set of data states are lower than verify voltages of the upper half of the set of data states; and
the lower half of the set of data states comprises an erased data state.

11. The apparatus of claim 1 , wherein:
the set of memory cells comprises memory cells which are configured to be assigned to a plurality of programmed data states and which are programmed to a plurality of intermediate threshold voltage distributions in the first program pass; and
a number of program pulses in the first set of program pulses is equal to a number of programmed data states in the plurality of programmed data states.

12. The apparatus of claim 1 , wherein:
the set of memory cells comprises memory cells which are configured to be assigned to a first programmed data state and which are programmed to a first intermediate threshold voltage distribution in response to a first program pulse of the first set of program pulses;
the set of memory cells comprises memory cells which are configured to be assigned to a second programmed data state and which are programmed to the first intermediate threshold voltage distribution in response to the first program pulse of the first set of program pulses; and
the memory cells which are configured to be assigned to the second programmed data state are programmed to a second intermediate threshold voltage distribution in response to a second program pulse of the first set of program pulses while the memory cells which are configured to be assigned to the first programmed data state are inhibited from being programmed.

13. The apparatus of claim 12 , wherein:
the set of memory cells comprises memory cells which are configured to be assigned to a third programmed data state and which are programmed to the first intermediate threshold voltage distribution in response to the first program pulse of the first set of program pulses;
the memory cells which are configured to be assigned to the third programmed data state are programmed to the second intermediate threshold voltage distribution in response to the second program pulse of the first set of program pulses; and
the memory cells which are configured to be assigned to the third programmed data state are programmed to a third intermediate threshold voltage distribution in response to a third program pulse of the first set of program pulses while the memory cells which are configured to be assigned to the first programmed data state and the memory cells which are configured to be assigned to the second programmed data state are inhibited from being programmed.

14. An apparatus, comprising:
a control circuit connected to a

Assignees

• Sandisk Technologies Llc

Inventors

• Baraskar Ashish
• Lu Ching-Huang
• DIEP Vinh
• Dong Yingda

Classifications

• G11C11/5642

  Sensing or reading circuits; Data output circuits · CPC title

• G11C16/3459

  Circuits or methods to verify correct programming of nonvolatile memory cells · CPC title

• G11C16/26

  Sensing or reading circuits; Data output circuits · CPC title

• G11C11/5628

  Programming or writing circuits; Data input circuits · CPC title

• G11C16/24

  Bit-line control circuits · CPC title