Three-dimensional memory device including a silicon-germanium source contact layer and method of making the same

Patent metadata

Field	Value
Publication number	US-11322509-B2
Application number	US-202017001270-A
Country	US
Kind code	B2
Filing date	Aug 24, 2020
Priority date	Dec 17, 2018
Publication date	May 3, 2022
Grant date	May 3, 2022

Abstract

A memory device includes a silicon-germanium source contact layer, an alternating stack of insulating layers and electrically conductive layers located over the silicon-germanium source contact layer, and a memory stack structure vertically extending through the alternating stack. The memory stack structure comprises a memory film and a vertical semiconductor channel that contacts the memory film. The silicon-germanium source contact layer contacts a cylindrical portion of an outer sidewall of the vertical semiconductor channel. Logic circuits for operating the memory elements may be provided on a substrate within a same semiconductor die, or may be provided in another semiconductor die that is bonded to the semiconductor die containing the memory device.

First claim

What is claimed is:

1. A bonded assembly comprising a memory die and a logic die, wherein: the memory die comprises:
a silicon-germanium source contact layer;
an alternating stack of insulating layers and electrically conductive layers located over the silicon-germanium source contact layer;
a two-dimensional array of memory stack structures vertically extending through the alternating stack, wherein each of the memory stack structures comprises a memory film and a silicon-germanium vertical semiconductor channel that contacts the memory film, and the silicon-germanium source contact layer contacts a cylindrical portion of an outer sidewall of the silicon-germanium vertical semiconductor channel of each of the memory stack structures;
memory-side dielectric material layers embedding memory-side metal interconnect structures and memory-side bonding pads; and
a first source-level silicon-germanium layer located on the silicon-germanium source contact layer and vertically spaced from the alternating stack by the silicon-germanium source contact layer, and the logic die comprises:
a peripheral circuit comprising semiconductor devices located on a logic-side substrate and configured to control operation of memory elements within the two-dimensional array of memory stack structures; and
logic-side bonding pads electrically connected to a respective node of the peripheral circuit and bonded to a respective one of the memory-side bonding pads.

2. The bonded assembly of claim 1 , wherein the memory die further comprises a silicon oxide encapsulation layer located on the first source-level silicon-germanium layer and having a grooved surface in which grooves are arranged in a grid pattern.

3. The bonded assembly of claim 1 , wherein the memory die further comprises an array of dielectric cap structures embedded in the first source-level silicon-germanium layer, wherein each of the dielectric cap structures includes a stack of at least a first dielectric plate and a second dielectric plate.

4. The bonded assembly of claim 3 , wherein:
each of the memory films comprises a layer stack including a charge storage layer and a tunneling dielectric layer;
each of the first dielectric plates has a same material composition and a same thickness as the charge storage layer; and
each of the second dielectric plates has a same material composition and a same thickness as the tunneling dielectric layer.

5. The bonded assembly of claim 1 , wherein the memory die further comprises a second source-level silicon-germanium layer located between the silicon-germanium source contact layer and the alternating stack.

6. The bonded assembly of claim 5 , wherein the memory die further comprises:
a backside trench fill structure contacting sidewalls of each layer within the alternating stack; and
a silicon-germanium oxide plate contacting a sidewall of the second source-level silicon-germanium layer and a surface of the silicon-germanium source contact layer.

7. The bonded assembly of claim 5 , wherein:
the silicon-germanium vertical semiconductor channels have a doping of a first conductivity type; and
the silicon-germanium source contact layer, the first source-level silicon-germanium layer, and the second source-level silicon-germanium layer have a doping of a second conductivity type that is an opposite of the first conductivity type.

8. The bonded assembly of claim 7 , wherein the silicon-germanium source contact layer differs in atomic concentration of germanium or in atomic concentration of electrical dopants from at least one the first source-level silicon-germanium layer and the second source-level silicon-germanium layer.

9. The bonded assembly of claim 5 , wherein the memory die further comprises:
a source-level insulating layer contacting a horizontal surface of the second source-level silicon-germanium layer; and
a source-select-level conductive layer contacting a horizontal surface of the source-level insulating layer and a horizontal surface of the alternating stack and comprising a doped semiconductor material that is different from a material of the electrically conductive layers.

10. The bonded assembly of claim 1 , wherein each of the memory films comprises a concave annular bottom surface that contacts a convex annular surface of the silicon-germanium source contact layer.

11. The bonded assembly of claim 1 , wherein the logic die further comprises logic-side dielectric material layers embedding logic-side metal interconnect structures and the logic-side bonding pads.

12. A method of forming a semiconductor structure, the method comprising forming a memory die by:
sequentially forming a disposable material layer, in-process source-level material layers, and an alternating stack of insulating layers and spacer material layers over a carrier substrate, wherein the in-process source-level material layers include a source-level sacrificial layer, and the spacer material layers are formed as, or are subsequently replaced with, electrically conductive layers;
forming memory stack structures vertically extending through the alternating stack, wherein each of the memory stack structures comprises a memory film and a silicon-germanium vertical semiconductor channel;
replacing the source-level sacrificial layer and an annular portion of each memory film with a silicon-germanium source contact layer, wherein the silicon-germanium source contact layer surrounds and contacts each of the vertical semiconductor channels; and
detaching an assembly including the silicon-germanium source contact layer, the insulating layers, the electrically conducive layers, and the memory stack structures from the carrier substrate by removing the disposable material layer.

13. The method of claim 12 , wherein the disposable material layer comprises a silicate glass material.

14. The method of claim 13 , further comprising:
forming a network of channel trenches within the disposable material layer; and
the method further comprises performing a wet etch process in which a wet etch chemical that etches a material of the disposable material layer is flowed into the network of channel trenches.

15. The method of claim 13 , further comprising:
forming a carrier-side silicon oxide layer comprising undoped silicate glass on the carrier substrate, wherein the disposable material layer comprises borosilicate glass and is formed on the carrier-side silicon oxide layer; and
forming a silicon oxide encapsulation layer comprising undoped silicate glass on the disposable material layer.

16. The method of claim 12 , wherein the disposable material layer comprises a semiconductor material containing germanium at an atomic concentration greater than 50%.

17. The method of claim 12 , further comprising:
forming memory-side metal interconnect structures and memory-side bonding pads that are embedded within memory-side dielectric material layers over the memory stack structures;
providing a logic die that comprises a peripheral circuit including semiconductor devices configured to control operation of the memory elements within the memory stack structures, and logic-side bonding pads electrically connected to a respective node of the peripheral circuit; and
attaching the logic die to the memory die by bonding the logic-side bonding pads to a respective one of the memory-side bonding pads.

18. The method of claim 12 , wherein:
the in-process source-level material layers include a first source-level silicon-germanium layer that is formed on the disposable material layer and a second source-le

Assignees

• Sandisk Technologies Llc

Inventors

• Baraskar Ashish
• Makala Raghuveer S
• Rabkin Peter

Classifications

• H10D84/038

  using silicon technology, e.g. SiGe · CPC title

• H10D84/016

  the components including vertical IGFETs · CPC title

• H10D84/013

  Manufacturing their source or drain regions, e.g. silicided source or drain regions · CPC title

• H10D62/292

  Non-planar channels of IGFETs (resulting from the gate electrode dispositions, e.g. within trenches H10D64/512) · CPC title

• H10D62/151

  of IGFETs  (of IGFETs having LDD or DDD structure H10D30/601; of thin film transistors H10D30/6713) · CPC title