Memory device with compensation for program speed variations due to block oxide thinning

Patent metadata

Field	Value
Publication number	US-11024387-B2
Application number	US-202017102712-A
Country	US
Kind code	B2
Filing date	Nov 24, 2020
Priority date	Jan 11, 2019
Publication date	Jun 1, 2021
Grant date	Jun 1, 2021

Abstract

Techniques are provided for optimizing a program operation in a memory device to compensate for program speed variations due to block oxide thinning. In one approach, during a program operation, a program voltage which indicates program speed is acquired from sub-blocks with the highest and lowest program speeds. An initial program voltage for intermediate sub-blocks can be determined based on the acquired program voltages and the positions of the intermediate sub-blocks. The technique can accommodate a loss of one or both acquired program voltages if the programming is interrupted. In another approach, a program voltage which indicates program speed is acquired from one sub-block, and for a later-programmed sub-block, an appropriate offset is located from a table and summed with the acquired program voltage to determine an optimum initial program voltage.

First claim

We claim:

1. An apparatus, comprising:
a plurality of memory cells arranged in NAND strings in a plurality of sub-blocks of a block, the NAND strings are arranged in rows in one sub-block of the plurality of sub-blocks, the NAND strings comprise a plurality of concentric layers, the concentric layers comprise a blocking oxide layer, and a thickness of the blocking oxide layer is different in different sub-blocks of the plurality of sub-blocks; and
a control circuit connected to the block, the control circuit is configured to:
during programming of memory cells of the one sub-block, determine a first program voltage which is applied to memory cells of one of the rows of the one sub-block when threshold voltages of the memory cells of the one of the rows exceed a verify voltage; and
determine a program parameter for programming another sub-block of the block based on the first program voltage and a position of the another sub-block in the block, wherein the one of the rows is a first distance from an edge of the block, and the another sub-block is a second distance, different than the first distance, from the edge of the block.

2. The apparatus of claim 1 , wherein:
the one sub-block is a first-programmed sub-block of the block.

3. The apparatus of claim 1 , wherein:
the program parameter comprises an initial program voltage.

4. The apparatus of claim 1 , wherein:
to determine the program parameter, the control circuit is configured to determine an offset voltage based on the first program voltage and the position of the another sub-block in the block.

5. The apparatus of claim 1 , wherein:
the one of the rows of the one sub-block is an edge row of the one sub-block.

6. The apparatus of claim 1 , wherein:
the thickness of the blocking oxide layer is different in different rows of the one sub-block.

7. The apparatus of claim 1 , wherein:
among the rows in the one sub-block, the one of the rows is closest to the edge of the block.

8. The apparatus of claim 1 , wherein:
the control circuit is configured to program the memory cells of the one sub-block to a plurality of programmed data states; and
the verify voltage is for a lowest data state of the plurality of programmed data states.

9. The apparatus of claim 1 , wherein:
the NAND strings are connected to a plurality of bit lines;
the one sub-block comprises a number n rows; and
NAND strings arranged in the one of the rows in the one sub-block are connected to every nth bit line among the plurality of bit lines.

10. An apparatus, comprising:
a control circuit configured to connect to a block of memory cells, the block comprising a plurality of memory cells arranged in NAND strings in a plurality of sub-blocks of the block, the NAND strings are arranged in rows in one sub-block of the plurality of sub-blocks, and the control circuit is configured to:
during programming of memory cells of the one sub-block, determine a first program voltage which is applied to memory cells of one of the rows of the one sub-block when threshold voltages of the memory cells of the one of the rows exceed a verify voltage; and
determine a program parameter for programming another sub-block of the block based on the first program voltage and a position of the another sub-block in the block, wherein the one of the rows is a first distance from an edge of the block, and the another sub-block is a second distance, different than the first distance, from the edge of the block.

11. The apparatus of claim 10 , wherein:
the NAND strings comprise a plurality of concentric layers, the concentric layers comprise a blocking oxide layer, and a thickness of the blocking oxide layer is different in different sub-blocks of the plurality of sub-blocks.

12. The apparatus of claim 10 , wherein:
the one sub-block is a first-programmed sub-block of the block.

13. The apparatus of claim 10 , wherein:
the program parameter comprises an initial program voltage.

14. The apparatus of claim 10 , wherein:
to determine the program parameter, the control circuit is configured to determine an offset voltage based on the first program voltage and the position of the another sub-block in the block.

15. The apparatus of claim 10 , wherein the control circuit is configured to:
during programming of memory cells of the one sub-block, determine a second program voltage which is applied to memory cells of another of the rows of the one sub-block when threshold voltages of the memory cells of the another of the rows exceed the verify voltage, wherein the one of the rows and the another of the rows are at different distances from the edge of the block; and
determine the program parameter for programming the another sub-block of the block based on the second program voltage.

16. A method, comprising:
programming memory cells of one sub-block among a plurality of sub-blocks of a block, the memory cells are arranged in rows of NAND strings;
during the programming, determining a first program voltage which is applied to memory cells of one of the rows when threshold voltages of the memory cells of the one of the rows exceed a verify voltage; and
determining a program parameter for programming another sub-block of the block based on the first program voltage and a position of the another sub-block in the block, wherein the one of the rows is a first distance from an edge of the block, and the another sub-block is a second distance, different than the first distance, from the edge of the block.

17. The method of claim 16 , wherein:
the NAND strings comprise a plurality of concentric layers, the concentric layers comprise a blocking oxide layer, and a thickness of the blocking oxide layer is different in different sub-blocks of the plurality of sub-blocks.

18. The method of claim 17 , wherein:
the thickness of the blocking oxide layer is different in different rows of the one sub-block.

19. The method of claim 16 , wherein:
the determining the program parameter comprises looking up an offset voltage based on the first program voltage and the position of another sub-block of the block, and adding the offset voltage to the first program voltage to obtain an initial program voltage for the another sub-block.

20. The method of claim 16 , further comprising:
during the programming, determining a second program voltage which is applied to memory cells of another of the rows when threshold voltages of the memory cells of the another of the rows exceed the verify voltage; and
determining the program parameter for programming another the sub-block of the block based on the second program voltage.

Assignees

• Sandisk Technologies Llc

Inventors

• Lu Ching-Huang
• Baraskar Ashish
• DIEP Vinh

Classifications

• G11C16/10 Primary

  Programming or data input circuits · CPC title

• G11C16/26

  Sensing or reading circuits; Data output circuits · CPC title

• G11C16/0483 Primary

  comprising cells having several storage transistors connected in series · CPC title

• G11C16/08

  Address circuits; Decoders; Word-line control circuits · CPC title

• G11C11/5628

  Programming or writing circuits; Data input circuits · CPC title