Memory device with compensation for erase speed variations due to blocking oxide layer thinning

Patent metadata

Field	Value
Publication number	US-10923197-B2
Application number	US-202016922037-A
Country	US
Kind code	B2
Filing date	Jul 7, 2020
Priority date	Feb 20, 2019
Publication date	Feb 16, 2021
Grant date	Feb 16, 2021

Abstract

Techniques are provided for optimizing an erase operation in a memory device to compensate for erase speed variations due to blocking oxide thinning In an erase operation for a block, the channels of NAND strings in different sub-blocks can be charged up by different amounts. One approach adjusts the control gate voltage of a first select gate transistor in a NAND string. This adjusts the amount of holes generated in the channel due to gate-induced drain leakage. Another approach adjusts the control gate voltage of additional select gate transistors in the NAND string to adjust the conductivity of the adjacent channel regions. Another approach applies different bit line voltages to different rows of NAND strings in each sub-block.

First claim

We claim:

1. An apparatus, comprising:
a control circuit configured to connect to a plurality of memory cells, the plurality of memory cells are arranged in NAND strings in a plurality of sub-blocks of a block, the plurality of sub-blocks comprise a central sub-block and an edge sub-block, each NAND string comprises a channel, and the control circuit is configured to:
in an erase operation for the block, charge up channels of NAND strings in the central sub-block to a higher voltage than a voltage to which channels of NAND strings in the edge sub-block are charged up.

2. The apparatus of claim 1 , wherein:
the NAND strings comprise a first select gate transistor at a drain-end of the NAND strings;
a pair of the sub-blocks have equal erase speeds; and
control gates of the first select gate transistors in the pair of the sub-blocks having equal erase speeds are connected to one another.

3. The apparatus of claim 1 , wherein:
the NAND strings comprise a blocking oxide layer; and
a thickness of the blocking oxide layer is less in the edge sub-block than in the central sub-block.

4. The apparatus of claim 1 , wherein:
to charge up the channels of the NAND strings in the central sub-block and to charge up the channels of the NAND strings in the edge sub-block, the control circuit is configured to apply a common erase voltage to the drain ends of the NAND strings in the central sub-block and to the drain ends of the NAND strings in the edge sub-block.

5. The apparatus of claim 1 , wherein:
the control circuit is on a different die than the plurality of memory cells.

6. The apparatus of claim 1 , wherein:
the NAND strings comprise a first select gate transistor at a drain-end of the NAND strings; and
the control circuit, to charge up the channels of the NAND strings in the central sub-block, is configured to apply a control gate voltage to the first select gate transistors in the NAND strings in the central sub-block and, to charge up the channels of the NAND strings in the edge sub-block, is configured to apply a control gate voltage to the first select gate transistors in the NAND strings in the edge sub-block which is higher than the control gate voltage applied to the first select gate transistors in the NAND strings in the central sub-block.

7. The apparatus of claim 6 , wherein:
each NAND string comprises a second select gate transistor adjacent to the first select gate transistor; and
during the charge up of the channels of the NAND strings in the central sub-block, the control circuit is configured to apply a common control gate voltage to the second select gate transistors in the edge sub-block and in the central sub-block.

8. The apparatus of claim 1 , wherein:
the NAND strings comprise a first select gate transistor at a drain-end of the NAND strings and a second select gate transistor adjacent to the first select gate transistor;
during the charge up of the channels of the NAND strings in the central sub-block, the control circuit is configured to apply a control gate voltage to the second select gate transistors in the central sub-block; and
during the charge up of the channels of the NAND strings in the edge sub-block, the control circuit is configured to apply a control gate voltage to the second select gate transistors in the edge sub-block which is higher than the control gate voltage applied to the second select gate transistors in the central sub-block.

9. The apparatus of claim 8 , wherein:
the charging up of the channels of the NAND strings in the plurality of sub-blocks occurs in a plurality of erase loops;
the control gate voltage applied to the second select gate transistors in the NAND strings in the edge sub-block is stepped up in the plurality of erase loops by a first step size; and
the control gate voltage applied to the second select gate transistors in the NAND strings in the central sub-block is stepped up in the plurality of erase loops by a second step size which is lower than the first step size.

10. The apparatus of claim 1 , wherein:
the NAND strings comprise a first select gate transistor at a drain-end of the NAND strings and a second select gate transistor adjacent to the first transistor;
in each NAND string, a control gate of the second select gate transistor is disconnected from a control gate of the first select gate transistor;
the control gates of the first select gate transistors in the edge sub-block are connected to the control gates of the first select gate transistors in the central sub-block; and
the control circuit is configured to, during the charging up of the channels of the NAND strings in the plurality of sub-blocks, apply a common control gate voltage to the first select gate transistors in the edge sub-block and to the first select gate transistors in the central sub-block for generating gate-induced drain leakage at the first select gate transistors in the edge sub-block and at the first select gate transistors in the central sub-block, respectively, and apply a control gate voltage to the second select gate transistors in the edge sub-block which is higher than a control gate voltage applied to the second select gate transistors in the central sub-block.

11. The apparatus of claim 10 , wherein:
after the charging up of the channels of the NAND strings in the plurality of sub-blocks, the control circuit is configured to determine one or more sub-blocks which have passed an erase-verify test and one or more sub-blocks which have not passed the erase-verify test and, in response to the determination, continue the erase operation for the one or more sub-blocks which have not passed the erase-verify test while inhibiting a further erasing of the one or more sub-blocks which have passed the erase-verify test.

12. An apparatus, comprising:
a circuit configured to connect to a plurality of memory cells, the plurality of memory cells are arranged in NAND strings in a block, the NAND strings are arranged in multiple rows comprising one row and another row, an edge of the block is closer to the one row than to the another row, and each NAND string comprises a channel; and
a memory interface connected to the circuit, the circuit is configured to issue a command via the memory interface in an erase operation for the block to charge up channels of NAND strings in the another row by a greater amount than an amount to which NAND strings in the one row are charged up.

13. The apparatus of claim 12 , wherein:
the block comprises a plurality of sub-blocks; and
the one row and the another row are in a common sub-block of the plurality of sub-blocks.

14. The apparatus of claim 13 , wherein:
the common sub-block is an edge sub-block, adjacent to an edge of the block.

15. The apparatus of claim 12 , wherein:
the circuit, to charge up the channels of the NAND strings in the another row by the greater amount than the amount to which the NAND strings in the one row are charged up, is configured to issue a command via the memory interface to apply an erase voltage to drain ends of the NAND strings in the another row which is higher than an erase voltage which is applied concurrently to drain ends of the NAND strings in the one row.

16. The apparatus of claim 12 , wherein:
the multiple rows of NAND strings each comprise a first select gate transistor at a drain-end of the multiple rows of NAND strings; and
control gates of the first select gate transistors are connected to one another.

17. The apparatus of claim 12 , wherein:
the NAND strings comprise a blocking oxide layer; and
a thickness of the

Assignees

• Sandisk Technologies Llc

Inventors

• Lu Ching-Huang
• Baraskar Ashish
• DIEP Vinh

Classifications

• G11C16/3445

  Circuits or methods to verify correct erasure of nonvolatile memory cells · CPC title

• G11C16/16

  for erasing blocks, e.g. arrays, words, groups · CPC title

• G11C16/3472

  Circuits or methods to verify correct erasure of nonvolatile memory cells whilst erasing is in progress, e.g. by detecting onset or cessation of current flow in cells and using the detector output to terminate erasure · CPC title

• G11C11/5635

  Erasing circuits · CPC title

• G11C16/0483 Primary

  comprising cells having several storage transistors connected in series · CPC title