Modified verify scheme for programming a memory apparatus

Patent metadata

Field	Value
Publication number	US-11244734-B2
Application number	US-201916728716-A
Country	US
Kind code	B2
Filing date	Dec 27, 2019
Priority date	Dec 27, 2019
Publication date	Feb 8, 2022
Grant date	Feb 8, 2022

Abstract

A memory apparatus and method of operation is provided. The apparatus includes memory cells coupled to a control circuit. The control circuit is configured to perform a first programming stage including iteratively programming each of the memory cells to first program states and verifying that the memory cells have a threshold voltage above one of a plurality of first verify voltages corresponding to the first program states. The first programming stage ends before all of the memory cells are verified thereby leaving a fraction of the memory cells below the one of the plurality of first verify voltages. The control circuit also performs a second programming stage including iteratively programming each of the memory cells to second program states and verifying that at least a predetermined number of the memory cells have the threshold voltage above one of a plurality of second verify voltages corresponding to the second program states.

First claim

What is claimed is:

1. An apparatus, comprising:
a plurality of memory cells;
a control circuit coupled to the plurality of memory cells and configured to:
perform a first programming stage including iteratively programming each of the plurality of memory cells to one of a plurality of first program states and verifying that one or more of the plurality of memory cells has a threshold voltage above one of a plurality of first verify voltages corresponding to the plurality of first program states and ending the first programming stage before all of the plurality of memory cells are verified thereby leaving a fraction of the plurality of memory cells below the one of a plurality of first verify voltages, and
perform a second programming stage including iteratively programming each of the plurality of memory cells to one of a plurality of second program states and verifying that at least a predetermined number of the plurality of memory cells each has the threshold voltage above one of a plurality of second verify voltages corresponding to the plurality of second program states.

2. The apparatus as set forth in claim 1 , wherein the control circuit is further configured to count a quantity of the one or more of the plurality memory cells having the threshold voltage above the one of the plurality of first verify voltages and continue programming and verifying and counting until the quantity is larger than a threshold quantity.

3. The apparatus as set forth in claim 2 , wherein the control circuit is further configured to determine the threshold quantity for each of the plurality of memory cells based on which of the plurality of second program states corresponds with each of the plurality of memory cells.

4. The apparatus as set forth in claim 3 , wherein the threshold voltage of each the plurality of memory cells is within a common range of threshold voltages and the plurality of second program states includes one or more lower program states having the threshold voltage being closer to zero volts and one or more upper program states having the threshold voltage being further from zero volts than the one or more lower program states and the threshold quantity used for the one or more lower program states is less than the threshold quantity used for the one or more upper program states.

5. The apparatus as set forth in claim 1 , wherein the fraction of the plurality of memory cells below the one of a plurality of first verify voltages is greater than one half of a total number of the plurality of memory cells.

6. The apparatus as set forth in claim 1 , wherein the plurality of memory cells are coupled to a plurality of word lines and the control circuit is further configured to iteratively:
select one of the plurality of word lines and set a first programming voltage for the first programming stage,
apply the first programming voltage to the one of the plurality of word lines that is selected,
select a first verification signal for one of the plurality of first program states and apply the first verification signal to the one of the plurality of word lines that is selected while determining whether the threshold voltage for each of the plurality of memory cells connected to the one of the plurality of word lines is above the one of the plurality of first verify voltages for the one of the plurality of first program states,
set a first lockout status for each of the plurality of memory cells determined to have the threshold voltage above the one of the plurality of first verify voltages for the one of the plurality of first program states,
increase the programming voltage and return to apply the first programming voltage to the one of the plurality of word lines that is selected,
determine whether there is another of the plurality of word lines to be programmed,
return to select one of the plurality of word lines and set the first programming voltage for the first programming stage in response to determining there is another of the plurality of word lines to be programmed, and
end the first programming stage before all of the plurality of memory cells are determined to have the threshold voltage above the one of the plurality of first verify voltages corresponding to the one the plurality of first program states for each of the plurality of memory cells.

7. The apparatus as set forth in claim 6 , wherein the control circuit is further configured to iteratively:
select one of the plurality of word lines and set a second programming voltage for the second programming stage,
apply the second programming voltage to the one of the plurality of word lines that is selected,
select a second verification signal for one of the plurality of second program states and apply the second verification signal to the one of the plurality of word lines that is selected while determining whether the threshold voltage for each of the plurality of memory cells connected to the one of the plurality of word lines is above the one of the plurality of second verify voltages for the one of the plurality of second program states,
set a second lockout status for each of the plurality of memory cells determined to have the threshold voltage above the one of the plurality of second verify voltages for the one of the plurality of second program states,
increase the second programming voltage and return to apply the second programming voltage to the one of the plurality of word lines that is selected,
determine whether there is another of the plurality of word lines to be programmed,
return to select one of the plurality of word lines and set the second programming voltage for the second programming stage in response to determining there is another of the plurality of word lines to be programmed, and
end the second programming stage once the predetermined number of the plurality of memory cells are determined to have the threshold voltage above the one of the plurality of second verify voltages corresponding to the one the plurality of second program states for each of the plurality of memory cells.

8. A controller in communication with a plurality of memory cells of a memory apparatus, the controller configured to:
instruct the memory apparatus to perform a first programming stage including iteratively programming each of the plurality of memory cells to one of a plurality of first program states and verifying that one or more of the plurality of memory cells has a threshold voltage above one of a plurality of first verify voltages corresponding to the plurality of first program states and ending the first programming stage before all of the plurality of memory cells are verified thereby leaving a fraction of the plurality of memory cells below the one of a plurality of first verify voltages; and
instruct the memory apparatus perform a second programming stage including iteratively programming each of the plurality of memory cells to one of a plurality of second program states and verifying that at least a predetermined number of the plurality of memory cells each has the threshold voltage above one of a plurality of second verify voltages corresponding to the plurality of second program states.

9. The controller as set forth in claim 8 , wherein the controller is further configured to instruct the memory apparatus to count a quantity of the one or more of the plurality memory cells having the threshold voltage above the one of the plurality of first verify voltages and instruct the memory apparatus to continue programming and verifying and counting until the quantity is larger than a threshold quantity.

10. The controller as set forth in claim 9 , wherein the controller is further configured to determine the threshold quantity for each o

Assignees

• Sandisk Technologies Llc

Inventors

• Baraskar Ashish
• Chin Henry
• Lu Ching-Huang

Classifications

• G11C29/42

  using error correcting codes [ECC] or parity check · CPC title

• G11C8/08

  Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines · CPC title

• G11C7/12

  Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines · CPC title

• G11C7/1087

  Data input latches · CPC title

• G11C7/10 Primary

  Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers · CPC title