Apparatuses and methods for increased reliability row hammer counts
US-12592271-B2 · Mar 31, 2026 · US
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Akamatsu Hiroshi patents
Akamatsu Hiroshi is listed as an inventor on 71 patents in our database. Major assignees and classification codes are summarized below.
| Metric | Value |
|---|---|
| Inventor | Akamatsu Hiroshi |
| Total patents | 71 |
| First publication | Oct 29, 2015 |
| Latest publication | Mar 31, 2026 |
Notable patents
Publications ranked by popularity score, then publication date.
Bus sharing for row hammer mitigation alert
US-2026018202-A1 · Jan 15, 2026 · US
Apparatuses and methods including dice latches in a semiconductor device
US-12394456-B2 · Aug 19, 2025 · US
Staggered Write Control for Dual-Interlocked Cells
US-2025218494-A1 · Jul 3, 2025 · US
Apparatuses and methods for shared row and column address buses
US-12346586-B2 · Jul 1, 2025 · US
Apparatuses for sense amplifier voltage control
US-12165695-B2 · Dec 10, 2024 · US
Circuitry including a level shifter and logic, configured to receive a power up reset signal, and associated methods, devices, and systems
US-12165693-B2 · Dec 10, 2024 · US
Concurrent compensation in a memory system
US-2024274720-A1 · Aug 15, 2024 · US
Apparatuses and methods for increased reliability row hammer counts
US-2024212738-A1 · Jun 27, 2024 · US
Apparatuses and methods for shared row and column address buses
US-2024192874-A1 · Jun 13, 2024 · US
Recent patents
Latest publications not already listed above.
Concurrent compensation in a memory system
US-11967356-B2 · Apr 23, 2024 · US
Command triggered power gating for a memory device
US-11935614-B2 · Mar 19, 2024 · US
Apparatuses for sense amplifier voltage control
US-2023360691-A1 · Nov 9, 2023 · US
Apparatuses and methods including dice latches in a semiconductor device
US-2023343376-A1 · Oct 26, 2023 · US
Charge transfer between gate terminals of sub-threshold current reduction circuit transistors and related apparatuses and methods
US-11777488-B2 · Oct 3, 2023 · US
Apparatuses and methods including dice latches in a semiconductor device
US-11727967-B2 · Aug 15, 2023 · US
Apparatuses and methods including dice latches in a semiconductor device
US-2023223059-A1 · Jul 13, 2023 · US
Generating memory array control signals
US-11687289-B2 · Jun 27, 2023 · US
Circuitry including a level shifter and logic, and associated methods, devices, and systems
US-2023178141-A1 · Jun 8, 2023 · US
Leakage current reduction in electronic devices
US-11658662-B2 · May 23, 2023 · US
Quarter match concurrent compensation in a memory system
US-11626154-B2 · Apr 11, 2023 · US
Boundary protection in memory
US-11615828-B2 · Mar 28, 2023 · US
Column selector architecture with edge mat optimization
US-11538516-B2 · Dec 27, 2022 · US
Quarter match concurrent compensation in a memory system
US-2022406359-A1 · Dec 22, 2022 · US
Concurrent compensation in a memory system
US-2022406358-A1 · Dec 22, 2022 · US
Command triggered power gating for a memory device
US-2022366943-A1 · Nov 17, 2022 · US
Column selector architecture with edge mat optimization
US-2022293163-A1 · Sep 15, 2022 · US
Command triggered power gating for a memory device
US-11423953-B2 · Aug 23, 2022 · US
Charge transfer between gate terminals of sub-threshold current reduction circuit transistors and related apparatuses and methods
US-2022216864-A1 · Jul 7, 2022 · US
Generating memory array control signals
US-2022188036-A1 · Jun 16, 2022 · US
Major assignees
Companies most often associated with this inventor's publications.
| Assignee | Patents |
|---|---|
| Micron Technology Inc | 71 |
Top CPC classifications
Most common classification codes across this inventor's patents.
| CPC | Patents |
|---|---|
| G11C11/408 | 17 |
| G11C11/4074 | 15 |
| G11C29/78 | 14 |
| G11C8/12 | 12 |
| G11C11/4076 | 12 |