Concurrent compensation in a memory system

Patent metadata

Field	Value
Publication number	US-11967356-B2
Application number	US-202117350305-A
Country	US
Kind code	B2
Filing date	Jun 17, 2021
Priority date	Jun 17, 2021
Publication date	Apr 23, 2024
Grant date	Apr 23, 2024

Abstract

An example apparatus may perform concurrent threshold voltage compensation in a memory array with distributed row redundancy. The example apparatus may include a memory cell array having a mat having a plurality of row sections that each include respective prime memory cell rows and a respective redundant memory cell row. The example apparatus may further include a row decoder configured to receive an access command and a prime row address. The row decoder may be configured to, in response to a determination that the prime row address matches a defective prime row address, concurrently initiate a threshold voltage compensation operation on both of a prime row of the respective plurality of prime rows of memory cells of a first row section of the plurality of row sections corresponding to the prime row address and the respective redundant row of a second row section of the plurality of row sections.

First claim

What is claimed is:

1. An apparatus comprising:
a memory cell array comprising a mat having a plurality of row sections, wherein each of the plurality of row sections includes respective prime memory cell rows and a respective redundant memory cell row; and
a row decoder configured to receive an access command and a prime row address, wherein the row decoder is configured to, in response to a determination that the prime row address matches a defective prime row address, concurrently initiate a threshold voltage compensation operation on both of a prime row of the respective plurality of prime rows of memory cells of a first row section of the plurality of row sections corresponding to the prime row address and the respective redundant row of a second row section of the plurality of row sections.

2. The apparatus of claim 1 , wherein the row decoder comprises a plurality of fuse latch and comparator circuits each corresponding to one of the respective redundant memory cell rows, wherein each of the fuse latch and comparator circuits are configured to compare the prime row address with a respective defective prime row address received via fuse array data to provide a respective match signal, wherein the row decoder is configured to select the second row section based on receipt of the respective match signal from a fuse data latch and comparator circuit of the plurality of fuse latch and comparator circuits corresponding to the respective redundant memory cell of the second row section.

3. The apparatus of claim 2 , wherein the row decoder further comprises a logic tree configured to provide a hit signal in response to a determination that at least one of the respective match signals of the plurality of fuse latch and comparator circuits is set, wherein, in response to the hit signal, the row decoder is configured to stop the concurrent threshold voltage compensation operation on the prime row prior to activation of a wordline corresponding to the prime row.

4. The apparatus of claim 3 , wherein the hit signal provided by the logic tree is delayed relative to the respective match signal.

5. The apparatus of claim 3 , wherein the logic tree includes cascading XOR gates to determine whether at least one of the respective match signals of the plurality of fuse latch and comparator circuits is set.

6. The apparatus of claim 2 , wherein a fuse latch and comparator circuit of the plurality of fuse latch and comparator circuits includes respective fuse latches configured to store a respective detective prime address received from a fuse array.

7. The apparatus of claim 1 , wherein the first row section and the second row sections are different sections.

8. The apparatus of claim 1 , wherein the first row section and the second row sections a same row section.

9. The apparatus of claim 1 , wherein the row decoder is configured to initiate the threshold voltage compensation operation only on the prime row in response to a determination that the prime row address lacks a matching defective prime row address.

10. An apparatus comprising:
a first plurality of fuse latch and comparator circuits each associated with a particular row section of a first plurality of row sections and configured to store a respective defective row address, wherein a first fuse latch and comparator circuit of the first plurality of fuse latch and comparator circuits is configured to, in response to a determination that a received prime row address matches the respective defective row address, provide a first match signal;
a second plurality of fuse latch and comparator circuits each associated with a particular row section of a second plurality of row sections and configured to store a respective defective row address, wherein a second fuse latch and comparator circuit of the second plurality of fuse latch and comparator circuits is configured to, in response to a determination that the received prime row address matches the respective defective row address, provide a second match signal;
a first predecoder coupled to the first plurality of fuse latch and comparator circuits and configured to receive the first match signal and to receive the prime row address, wherein, in response to the first match signal, cause a first threshold voltage compensation to be initiated on a first redundant row associated with the first fuse latch and comparator circuit, wherein, in response to a determination that the decoded prime row address targets a first prime row of the first plurality of row sections, cause a second threshold voltage compensation operation to be initiated on the first prime row; and
a second predecoder coupled to the second plurality of fuse latch and comparator circuits and configured to receive the second match signal and to receive the prime row address, wherein, in response to the first match signal, cause a third threshold voltage compensation to be initiated on a second redundant row associated with the second fuse latch and comparator circuit, wherein, in response to a determination that the decoded prime row address targets a second prime row of the second plurality of row sections, cause a fourth threshold voltage compensation operation to be initiated on the second prime row, wherein at least one of the first or third threshold voltage compensation operations is at least partially concurrent with at least one of the second or fourth threshold voltage compensation operations.

11. The apparatus of claim 10 , wherein each of the first plurality of fuse latch and comparator circuits is associated with a redundant row of a respective one of the first plurality of row sections, wherein each of the second plurality of fuse latch and comparator circuits is associated with a redundant row of a respective one of the second plurality of row sections.

12. The apparatus of claim 10 , further comprising a logic tree configured to provide a hit signal in response to a determination that at least one respective match signal of the first or second plurality of fuse latch and comparator circuits is set, wherein, in response to the hit signal, the first predecoder is configured to stop the second concurrent threshold voltage compensation operation on the first prime row, wherein, in response to the hit signal, the second predecoder is configured to stop the second concurrent threshold voltage compensation operation on the second prime row.

13. The apparatus of claim 12 , wherein the hit signal provided by the logic tree is delayed relative to the first and second match signals.

14. The apparatus of claim 10 , wherein the first fuse latch and comparator circuit includes respective fuse latches configured to store the respective detective prime address received from a fuse array.

15. The apparatus of claim 10 , wherein the first predecoder is configured to skip initiation of the first threshold voltage compensation operation when the first match signal provided from the first fuse latch and comparator circuit indicates that the prime row address is different than the respective defective row address.

16. A method comprising:
receiving a prime row address associated with an access operation at a first plurality of fuse latch comparator circuits, a second plurality of fuse latch comparator circuits, a first predecoder, and a second predecoder, wherein each of the first plurality of fuse latch and comparator circuits is associated with a particular row section of a first plurality of row sections and each of the second plurality of fuse latch and comparator circuits is associated with a particular row section of a second plurality of row sections;
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Assignees

• Micron Technology Inc

Inventors

• Akamatsu Hiroshi
• Choi Wonjun
• Rice Jacob
• Yoshida Kenji

Classifications

• H10D84/133

  the built-in components being capacitors or resistors · CPC title

• H10D62/8503

  Nitride Group III-V materials, e.g. AlN or GaN · CPC title

• H10D30/6755

  Oxide semiconductors, e.g. zinc oxide, copper aluminium oxide or cadmium stannate · CPC title

• H10D30/6713

  characterised by the properties of the source or drain regions, e.g. compositions or sectional shapes · CPC title

• H10D30/0415

  of FETs having ferroelectric gate insulators · CPC title