Apparatuses and methods including dice latches in a semiconductor device

Patent metadata

Field	Value
Publication number	US-11727967-B2
Application number	US-202217575378-A
Country	US
Kind code	B2
Filing date	Jan 13, 2022
Priority date	Jan 13, 2022
Publication date	Aug 15, 2023
Grant date	Aug 15, 2023

Abstract

Apparatuses and methods including dice latches in a semiconductor device are disclosed. Example dice latches have a circuit arrangement that include a reduced number of circuits, such as transistors, and provides a compact layout. Operation of example dice latches and other dice latches may be controlled by separately provided control signals for loading and latching of data, and in some examples, for a reset operation. Example layouts include circuit elements aligned along a direction with at least one other circuit element offset from the other aligned circuit elements.

First claim

What is claimed is:

1. An apparatus, comprising:
first, second, third, and fourth data nodes;
first, second, third, and fourth data node switches, each data node switch coupled to a respective one of the first, second, third, and fourth data nodes, the first and second data node switches configured to provide when activated a first data to the first and second data nodes, respectively, and the third and fourth data node switches configured to provide when activated a second data to the third and fourth data nodes, respectively;
first, second, third, and fourth pull-up circuits, each pull-up circuit configured to pull-up a respective one of the first, second, third, and fourth data nodes to a first voltage when activated; and
first, second, third, and fourth pull-down circuits, each pull-down circuit configured to pull-down a respective one of the first, second, third, and fourth data nodes to a second voltage when activated,
wherein the first pull-up circuit is activated based on voltage of the fourth data node, the second pull-up circuit is activated based on a voltage of the third data node, the third pull-up circuit is activated based on a voltage of the first data node, and the fourth pull-up circuit is activated based on a voltage of the second data node, and
wherein the first pull-down circuit is activated based on the voltage of the third data node, the second pull-down circuit is activated based on the voltage of the fourth data node, the third pull-down circuit is activated based on the voltage of the second data node, and the fourth pull-down circuit is activated based on the voltage of the first data node.

2. The apparatus of claim 1 , further comprising:
a first reset circuit coupled to the third pull-down circuit and configured to receive the second voltage; and
a second reset circuit coupled to the fourth pull-down circuit and configured to receive the second voltage,
wherein the first and second reset circuits are configured to prevent the second voltage from being provided to the third and fourth data nodes, respectively, responsive to an active reset signal.

3. The apparatus of claim 1 wherein the first, second, third, and fourth data node switches, the first, second, third, and fourth pull-up circuits, and the first, second, third, and fourth pull-down circuits are arranged in groups of transistors, wherein a plurality of the groups of transistors are arranged along a first direction, and at least one group of the groups of transistors is arranged with an offset along a second direction from the plurality of the groups of transistors arranged along the first direction.

4. The apparatus of claim 3 wherein each group of transistors comprises:
one of the pull-up circuits or one of the pull-down circuits; and
another one of the pull-up circuits, another one of the pull-down circuits, or one of the data node switches.

5. The apparatus of claim 3 wherein the groups of transistors comprise:
a first plurality of groups of transistors including transistors of a first conductivity type; and
a second plurality of groups of transistors including transistors of a second conductivity type,
wherein each group of transistors of the first plurality of groups of transistors includes one of the first, second, third, and fourth pull-down circuits and one of the first, second, third, and fourth data node switches, and
wherein each group of transistors of the second plurality of groups of transistors includes two of the first, second, third, and fourth pull-up circuits.

6. The apparatus of claim 5 wherein the first plurality of groups of transistors are arranged along the first direction and at least one of the second plurality of groups of transistors is arranged with the offset along the second direction from the first plurality of groups of transistors arranged along the first direction.

7. The apparatus of claim 3 wherein the group of transistors comprises:
a first group of transistors including the fourth data node switch and the fourth pull-down circuit;
a second group of transistors including the second data node switch and the second pull-down circuit;
a third group of transistors including the third data node switch and the third pull-down circuit;
a fourth group of transistors including the first data node switch and the first pull-down circuit;
a fifth group of transistors including the first pull-up circuit and the fourth pull-up circuit; and
a sixth group of transistors including the second pull-up circuit and the third pull-up circuit,
wherein the first, second, third, fourth, and fifth groups of transistors are arranged along the first direction and the sixth group of transistors is arranged with an offset along the second direction from the first, second, third, fourth, and fifth groups of transistors arranged along the first direction.

8. The apparatus of claim 7 , further comprising:
a first reset circuit coupled to the third pull-down circuit and configured to receive the second voltage; and
a second reset circuit coupled to the fourth pull-down circuit and configured to receive the second voltage,
wherein the first group of transistors further includes the second reset circuit and the third group of transistors further includes the first reset circuit.

9. The apparatus of claim 1 wherein the first, second, third, and fourth data node switches and the first, second, third, and fourth pull-down circuits each comprise an n-channel transistor and wherein the first, second, third, and fourth pull-up circuits each comprise a p-channel transistor.

10. The apparatus of claim 9 wherein the n-channel transistors of the first, second, third, and fourth data node switches, and the first, second, third, and fourth pull-down circuits are arranged in groups of transistors, each of the groups of transistors including one of the data node switches and one of the pull-down circuits.

Assignees

• Micron Technology Inc

Inventors

• Riho Yoshiro
• Akamatsu Hiroshi
• Long Jian
• Werhane Kevin G
• Liu Liang
• Fujiwara Yoshinori

Classifications

• H03K3/037

  Bistable circuits · CPC title

• G11C29/12 Primary

  Built-in arrangements for testing, e.g. built-in self testing [BIST] {or interconnection details} · CPC title

• G11C7/1087 Primary

  Data input latches · CPC title

• G11C11/4125 Primary

  Cells incorporating circuit means for protecting against loss of information · CPC title

• G11C19/28

  using semiconductor elements (G11C19/14, G11C19/36 take precedence) · CPC title