Generating memory array control signals

Patent metadata

Field	Value
Publication number	US-2022188036-A1
Application number	US-202117559469-A
Country	US
Kind code	A1
Filing date	Dec 22, 2021
Priority date	May 18, 2020
Publication date	Jun 16, 2022
Grant date	—

Abstract

Methods, systems, and devices for generating memory array control signals are described. A timing component may be configured to generate signals for operating a memory array. The timing component may include first logic that indicates when input signals are different, second logic that indicates when at least one of the input signals has a particular state, and third logic that indicates when the input signals have the same state. The output of the second logic and third logic may be controllable by other input signals. An output of the timing component may be set by one of the input signals and reset by the other input signals using the first logic, second logic, and third logic.

First claim

1 . (canceled)

2 . An apparatus, comprising:
a signal driver comprising:
a first driver comprising combinational logic configured to obtain a first control signal based at least in part on a first delay signal and a second delay signal, wherein first logic of the combinational logic is configured to indicate when the first delay signal and the second delay signal have different states, second logic of the combinational logic is configured to indicate when at least one of the first delay signal or the second delay signal have a first state, and third logic of the combinational logic is configured to indicate when the first delay signal and the second delay signal have a same state;
a second driver configured to obtain a second control signal based at least in part on a third delay signal and a fourth delay signal; and
logic coupled with the first driver and the second driver and configured to combine the first control signal and the second control signal to obtain a signal for operating a memory array.

3 . The apparatus of claim 2 , wherein the logic comprises:
an AND gate coupled with an output of the first driver, and an inverter coupled with the AND gate and an output of the second driver.

4 . The apparatus of claim 3 , wherein the logic further comprises:
an inverted OR gate that is coupled with an output of the AND gate, and an input that is coupled with the inverted OR gate, the input configured to receive a signal for indicating whether the memory array is configured in an operating mode or a testing mode.

5 . The apparatus of claim 4 , further comprising:
a second inverter coupled with an output of the inverted OR gate and configured to generate the signal for operating the memory array.

6 . The apparatus of claim 2 , wherein:
fourth logic of the combinational logic is configured to invert an output of the third logic of the combinational logic, wherein the fourth logic of the combinational logic is further configured to generate the first control signal.

7 . The apparatus of claim 2 , wherein:
an output of the second logic of the combinational logic is based at least in part on a signal for overriding an output of the first logic of the combinational logic; and the third logic of the combinational logic is configured to set the first control signal to the first state based at least in part on the signal being configured to override the output of the first logic of the combinational logic.

8 . The apparatus of claim 2 , wherein:
an output of the second logic of the combinational logic is configured to be set to a second state based at least in part on a signal indicating that the first logic of the combinational logic is disabled.

9 . The apparatus of claim 2 , wherein:
the second driver comprises second combinational logic, first logic of the second combinational logic is configured to indicate when the third delay signal and the fourth delay signal have different states, second logic of the second combinational logic is configured to indicate when at least one of the third delay signal or the fourth delay signal have the first state, wherein an output of the second logic of the second combinational logic is configured to be set to a second state based at least in part on an signal indicating that the first logic of the second combinational logic is disabled, and third logic of the second combinational logic is configured to indicate when the third delay signal and the fourth delay signal have a same state, wherein the third logic of the second combinational logic is configured to set the second control signal to the first state based at least in part on the signal indicating that the first logic of the second combinational logic is disabled.

10 . An apparatus, comprising:
first logic, wherein a first input of the first logic is coupled with an exclusive OR gate of the first logic and a first inverter of the first logic, and wherein a second input of the first logic is coupled with the exclusive OR gate of the first logic and a second inverter of the first logic; second logic, wherein a first input of the second logic is coupled with an AND gate of the second logic, wherein a second input of the second logic is coupled with the AND gate of the second logic, and wherein a third input of the second logic is coupled with an inverter of the second logic and an inverted OR gate of the second logic; and third logic, wherein a first input of the third logic is coupled with an AND gate of the third logic and the exclusive OR gate of the first logic, wherein a second input of the third logic is coupled with the AND gate of the third logic and the inverted OR gate of the second logic, and wherein a third input of the third logic is coupled with the AND gate of the third logic and the inverter of the second logic.

11 . The apparatus of claim 10 , wherein:
a first input of the exclusive OR gate of the first logic is coupled with the first input of the first logic, a second input of the exclusive OR gate of the first logic is coupled with an output of the first inverter of the first logic, a third input of the exclusive OR gate of the first logic is coupled with the second input of the first logic, and a fourth input of the exclusive OR gate of the first logic is coupled with an output of the second inverter of the first logic.

12 . The apparatus of claim 11 , wherein:
the second input of the exclusive OR gate of the first logic is coupled, via the first input of the second logic, with a first input of the AND gate of the second logic, and the fourth input of the exclusive OR gate of the first logic is coupled, via the second input of the second logic, with a second input of the AND gate of the second logic.

13 . The apparatus of claim 10 , wherein:
a first input of the inverted OR gate of the second logic is coupled with an output of the AND gate of the second logic, a second input of the inverted OR gate of the second logic is coupled with the third input of the second logic and the inverter of the second logic, and the third input of the second logic is configured to receive a signal for overriding an output of the first logic.

14 . The apparatus of claim 10 , wherein:
a first input of the AND gate of the third logic is coupled with an output of the exclusive OR gate of the first logic, a second input of the AND gate of the third logic is coupled with an output of the inverted OR gate of the second logic, and a third input of the AND gate of the third logic is coupled with an output of the inverter of the second logic.

15 . The apparatus of claim 10 , wherein an inverted OR gate of the third logic is coupled with the AND gate of the third logic.

16 . The apparatus of claim 15 , wherein:
a first input of the inverted OR gate of the third logic is coupled with an output of the AND gate of the third logic, and a second input of the inverted OR gate of the third logic is coupled with a fourth input of the third logic configured to receive a signal for configuring a memory array in an operating mode or a testing mode.

17 . The apparatus of claim 10 , further comprising:
fourth logic, wherein a first input of the fourth logic is coupled with the inverted OR gate of the third logic and an inverter of the fourth logic.

18 . An apparatus, comprising:
a first driver comprising first combinational logic configured to generate a first signal for operating a memory array based at least in part on a first delay signal and a second delay signal, wherein first logic of the first combinational logic i

Assignees

• Micron Technology Inc

Inventors

• Akamatsu Hiroshi

Classifications

• G11C7/22 Primary

  Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management · CPC title

• G11C7/222

  Clock generating, synchronizing or distributing circuits within memory device · CPC title

• G11C7/106

  Data output latches · CPC title

• G11C7/1087

  Data input latches · CPC title

• G06F3/0683

  Plurality of storage devices · CPC title