Column selector architecture with edge mat optimization

Patent metadata

Field	Value
Publication number	US-2022293163-A1
Application number	US-202217832097-A
Country	US
Kind code	A1
Filing date	Jun 3, 2022
Priority date	Oct 29, 2020
Publication date	Sep 15, 2022
Grant date	—

Abstract

A memory mat architecture is presented where a column decoder is disposed within the memory array. The location of the column decoder reduces a distance between the column decoder and a target memory cell and thus reduces a distance that a column select signal travels from the column decoder to the target memory cell. A single predecoder is disposed in a bank controller for the memory array. The column decoder may be disposed in the middle of the memory array or offset from the middle near the far edge of the memory array opposite the bank controller. The location of the column decoder enables a reduced array access time to obtain data from the target memory cell.

First claim

What is claimed is:

1 . An electronic device comprising:
a section decoder configured to determine one of a first section and a second section of a memory bank for a location of a target memory cell based on a row address of the target memory cell, wherein a column decoder is disposed between the first section and the second section, and wherein the first section comprises at least two edge memory mats and at least one inner memory mat, and wherein the first section is adjacent to a bank controller of the memory bank; and a mode register configured to identify a mode of a speed of a column select operation, wherein the mode includes high or low, and wherein the electronic device is configured to select a voltage level to drive the column decoder based on the mode of the speed and the location of the target memory cell, and wherein the electronic device is configured to determine a process corner for the column select operation.

2 . The electronic device of claim 1 , wherein the electronic device is configured to select the voltage level to drive the column decoder from a plurality of levels at least based on the location of the target memory cell is in the second section of the memory bank.

3 . The electronic device of claim 1 , wherein the electronic device is configured to select the voltage level to drive the column decoder from a plurality of levels at least based on the mode of the speed is high.

4 . The electronic device of claim 1 , wherein the electronic device is configured to select the voltage level based on the process corner of the column select operation.

5 . The electronic device of claim 4 , wherein the process corner is at least one of fast-fast, typical-typical, and slow-slow.

6 . The electronic device of claim 5 , wherein the voltage level of the fast-fast process corner is about 1.2 volts, wherein the voltage level of the typical-typical process corner is about 1.4 volts, and wherein the voltage level of the slow-slow process corner is about 1.6 volts.

7 . The electronic device of claim 4 , wherein the electronic device is configured to select the voltage level based on the process corner, upon determining that the location of the target memory cell is in the second section and upon determining that the speed of the column select operation is high.

8 . The electronic device of claim 1 , wherein the electronic device is configured to select the voltage level as a baseline voltage of about 1.0 volts, upon determining that the location of the target memory cell is in the first section or upon determining the mode of the speed of the column select operation is low.

9 . The electronic device of claim 1 , wherein the electronic device comprises a multiplexer.

10 . The electronic device of claim 1 , wherein the electronic device comprises a process monitor configured to determine a value of the voltage level to drive the column decoder.

11 . A method comprising:
determining a location of a target memory cell based on a row address of the target memory cell, wherein the location is one of a first section and a second section of a memory bank, wherein a column decoder is disposed between the first section and the second section, and wherein the first section comprises at least two edge memory mats and at least one inner memory mat, and wherein the first section is adjacent to a bank controller of the memory bank; identifying a mode of a speed of a column select operation to be performed on the column decoder, wherein the mode includes high or low; determining a process corner for the column select operation; and selecting a voltage level to drive the column decoder based on the mode of the speed and the location of the target memory cell.

12 . The method of claim 11 , wherein the selecting the voltage level is based on the process corner of the column select operation.

13 . The method of claim 12 , wherein the selecting the voltage level is via a process monitor configured to determine a value of the voltage level to drive the column decoder, based on the process corner of the column select operation.

14 . The method of claim 13 , wherein the process monitor is communicatively coupled to a multiplexer to output the voltage level.

15 . A method comprising:
determining a process corner of a column select operation; identifying a voltage level corresponding to the process corner; and driving a column decoder via the voltage level, wherein the column decoder is disposed between a first section of a memory bank and a second section of the memory bank, wherein the first section comprises at least two edge memory mats and at least one inner memory mat, and wherein the first section is adjacent to a bank controller of the memory bank.

16 . The method of claim 15 , wherein the process corner is at least one of fast-fast, typical-typical, and slow-slow.

17 . The method of claim 16 , wherein the voltage level of the fast-fast process corner is about 1.2 volts, wherein the voltage level of the typical-typical process corner is about 1.4 volts, and wherein the voltage level of the slow-slow process corner is about 1.6 volts.

18 . The method of claim 15 , comprising:
identifying a location of a target memory cell based on a row address of the target memory cell; and identifying a mode of a speed of the column select operation, wherein the mode includes high or low.

19 . The method of claim 18 , comprising, upon determining that the location of the target memory cell is in the first section or upon determining the speed of the column select operation is low, driving the column decoder with a baseline voltage of about 1.0 volts.

20 . The method of claim 18 , comprising, upon determining that the location of the target memory cell is in the second section and upon determining that the speed of the column select operation is high, driving the column decoder with the voltage level based on the process corner.

Assignees

• Micron Technology Inc

Inventors

• He Yuan
• Akamatsu Hiroshi

Classifications

• G11C11/4093

  Input/output [I/O] data interface arrangements, e.g. data buffers · CPC title

• G11C11/4076

  Timing circuits (for regeneration management G11C11/406) · CPC title

• G11C11/4091

  Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating · CPC title

• G11C11/4097

  Bit-line organisation, e.g. bit-line layout, folded bit lines · CPC title

• G11C29/028

  with adaption or trimming of parameters · CPC title