Circuitry including a level shifter and logic, configured to receive a power up reset signal, and associated methods, devices, and systems

Patent metadata

Field	Value
Publication number	US-12165693-B2
Application number	US-202117457570-A
Country	US
Kind code	B2
Filing date	Dec 3, 2021
Priority date	Dec 3, 2021
Publication date	Dec 10, 2024
Grant date	Dec 10, 2024

Abstract

A device may include a level shifter including an at least one input and at least one output. The device may also include a logic circuit coupled to an output of the at least one output of the level shifter and configured to receive a power up reset signal. The logic circuit may be configured to isolate an output of the logic circuit from a supply voltage responsive to the power up reset signal and during at least a portion of a power up sequence. Associated circuits, systems, and methods are also disclosed.

First claim

What is claimed is:

1. A device, comprising:
a level shifter including an at least one input and at least one output; and
a logic circuit coupled to an output of the at least one output of the level shifter and configured to:
receive, independent of the level shifter, a power up reset signal responsive to a power up sequence;
isolate, during at least a portion of the power up sequence, an output of the logic circuit from a supply voltage responsive to the power up reset signal; and
couple, after the power up sequence, the output of the logic circuit to the supply voltage in response to a signal at the output of the level shifter.

2. The device of claim 1 , wherein logic circuit comprises:
a first transistor having a first terminal coupled to the supply voltage and a gate configured to receive the power up reset signal;
a second transistor having a gate coupled to the output of the level shifter, a first terminal coupled to a second terminal of the first transistor and a second terminal coupled to a node;
a third transistor having a gate coupled to the output of the level shifter, a first terminal coupled to the node, and a second terminal coupled to a reference voltage; and
a fourth transistor having a gate configured to receive the power up reset signal, a first terminal coupled to the node, and a second terminal coupled to the reference voltage.

3. The device of claim 2 , wherein the first transistor and the second transistor are PMOS transistor and the third transistor and the fourth transistor are NMOS transistors.

4. The device of claim 1 , wherein the level shifter is configured to receive the power up reset signal and an inverse power up reset signal.

5. The device of claim 1 , further comprising a word line driver including each of the level shifter and the logic circuit.

6. The device of claim 1 , wherein an output of the at least one output of the level shifter transitions from HIGH to LOW in response to an input of the at least one input of the level shifter transitioning from HIGH to LOW.

7. The device of claim 1 , wherein the at least one input of the level shifter includes a first input for receiving an input signal and a second input for receiving an inverse of the power up reset signal, wherein the at least one output of the level shifter includes a first output for generating a first output signal and a second output for generating a second output signal, the second output signal being an inverse of the first output signal.

8. A method of operating a memory device, comprising:
generating, via a level shifter, an output signal responsive to an input signal;
receiving, at a logic circuit, the output signal;
receiving, at the logic circuit and independent of the level shifter, a power up reset signal responsive to initiation of a power up sequence;
isolating an output of the logic circuit from a supply voltage during at least a portion of the power up sequence; and
coupling, after the power up sequence, the output of the logic circuit to the supply voltage based on the output signal.

9. The method of claim 8 , wherein receiving, at the logic circuit, the power up reset signal comprises receiving the power up reset signal at a PMOS transistor coupled to the supply voltage.

10. The method of claim 9 , wherein receiving, at the logic circuit, the power up reset signal further comprises receiving the power up reset signal at an NMOS transistor coupled to ground.

11. The method of claim 8 , wherein receiving, at the logic circuit, the output signal comprises receiving the output signal at a gate of each of a PMOS transistor and an NMOS transistor.

12. The method of claim 8 , wherein generating, via the level shifter, the output signal responsive to the input signal comprises generating, via the level shifter of a main word line driver, the output signal responsive to the input signal.

13. The method of claim 8 , wherein isolating the output of the logic circuit from the supply voltage comprises turning OFF a PMOS transistor coupled between the output of the logic circuit and the supply voltage.

14. The method of claim 8 , further comprising coupling the output of the logic circuit to ground.

15. The method of claim 8 , wherein isolating the output of the logic circuit from the supply voltage comprises isolating the output of the logic circuit from the supply voltage responsive to a voltage level of the power up reset signal increasing to a level to cause a PMOS transistor coupled between the output of the logic circuit and the supply voltage to turn OFF.

16. A system, comprising:
at least one input device;
at least one output device;
at least one processor device operably coupled to the input device and the output device; and
at least one memory device operably coupled to the at least one processor device and including a main word line driver, the main word line driver including:
a level shifter including an input and an output;
a first transistor having a first terminal coupled to a voltage supply and a gate configured to receive a power up reset signal;
a second transistor having a gate coupled to the output of the level shifter, a first terminal coupled to a second terminal of the first transistor and a second terminal coupled to a node;
a third transistor having a gate coupled to the output of the level shifter, a first terminal coupled to the node, and a second terminal coupled to a reference voltage; and
a fourth transistor having a gate configured to receive the power up reset signal, a first terminal coupled to the node, and a second terminal coupled to the reference voltage.

17. The system of claim 16 , the first transistor and the second transistor comprising PMOS transistor and the third transistor and the fourth transistor comprising NMOS transistors.

18. The system of claim 16 , the level shifter further configured to receive the power up reset signal and an inverse power up reset signal.

19. The system of claim 16 , wherein collectively the first transistor, the second transistor, the third transistor, and the fourth transistor are configured to operate as a NOR gate.

20. The system of claim 16 , wherein the output of the level shifter transitions from HIGH to LOW in response to the input of the level shifter transitioning from HIGH to LOW.

Assignees

• Micron Technology Inc

Inventors

• Akamatsu Hiroshi
• Ma Yantao

Classifications

• G11C11/4093

  Input/output [I/O] data interface arrangements, e.g. data buffers · CPC title

• H03K3/037

  Bistable circuits · CPC title

• H03K19/018521 Primary

  of complementary type, e.g. CMOS · CPC title

• G11C5/145

  Applications of charge pumps; Boosted voltage circuits; Clamp circuits therefor (G11C5/141 takes precedence) · CPC title

• G11C8/08 Primary

  Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines · CPC title