Quarter match concurrent compensation in a memory system

Patent metadata

Field	Value
Publication number	US-11626154-B2
Application number	US-202117350325-A
Country	US
Kind code	B2
Filing date	Jun 17, 2021
Priority date	Jun 17, 2021
Publication date	Apr 11, 2023
Grant date	Apr 11, 2023

Abstract

An example apparatus may perform concurrent threshold voltage compensation in a memory array with distributed row redundancy. The example apparatus may include a row decoder configured to configured to, in response to a determination that the prime row address matches a defective prime row address, concurrently initiate a threshold voltage compensation operation on both of a prime row of the respective plurality of prime rows of memory cells of a first row section of the plurality of row sections corresponding to the prime row address and the respective redundant row of a second row section of the plurality of row sections. The row decoder may be further configured to stop an access operation associated with the prime row from proceeding based on a comparison of subset of match signals from either the first or second pluralities of row sections.

First claim

What is claimed is:

1. An apparatus comprising:
a first plurality of defective row address comparison circuits each associated with a respective row section of a first plurality of row sections of a memory array and configured to store a respective defective prime row address, wherein each of the first plurality of defective row address comparison circuits are configured to compare a received prime row address with the stored respective defective prime row address to provide a respective match signal;
a second plurality of defective row address comparison circuits each associated with a respective row section of a second plurality of row sections of the memory array and configured to compare the received prime row address with a respective defective prime row address to provide a respective match signal;
a logic tree configured to compare the respective hit signals from the first plurality of row address comparison circuits to provide a first fast hit signal and to compare the respective hit signals from the second plurality of row address comparison circuits to provide a second fast hit signal, wherein the logic tree is further configured to compare the first and second fast hit signals to provide a hit signal;
a row decoder comprising a first predecoder associated with the first plurality of row sections and a second predecoder associated with the second plurality of row sections, wherein, during an access operation:
the first predecoder is configured to cause a first threshold voltage compensation operation to be initiated on a respective redundant row of a first row section of the first plurality of row sections associated with the respective hit signal provided by one of the first plurality of defective row address comparison circuits in response to the respective hit signal indicating that a prime row address matches the respective defective prime row address; and
the second predecoder is configured to, concurrent with the first threshold voltage compensation operation, cause a second threshold voltage compensation operation to be initiated on a prime row of a second row section of the second plurality of row sections when the prime row of the second row section of the second plurality of row sections corresponds to the prime row address, wherein the second predecoder is further configured to prevent an access operation associated with the prime row from proceeding in response to the first fast hit signal.

2. The apparatus of claim 1 , further comprising a first and second pluralities of defective row address latch circuits each associated with a respective row section of the first and second pluralities of row sections, respectively, and configured to latch the respective defective prime row address.

3. The apparatus of claim 1 , wherein the second predecoder is configured to stop the access operation associated with the prime row in response to the hit signal.

4. The apparatus of claim 3 , wherein the logic tree causes the first fast hit signal to indicate a hit before the hit signal.

5. The apparatus of claim 1 , wherein the second predecoder is configured to prevent activation of a word line coupled to the prime row in response to the first fast hit signal.

6. The apparatus of claim 1 , further comprising a main wordline driver configured to receive a signal from the second predecoder to control activation of a main wordline coupled to the wordline.

7. The apparatus of claim 1 , further comprising a subwordline driver circuit configured to receive a signal from the second predecoder to control activation of the wordline.

8. The apparatus of claim 1 , wherein the second predecoder is configured to cause the first threshold voltage compensation operation to be initiated on a respective redundant row of a third row section of the second plurality of row sections associated with the respective hit signal provided by one of the second plurality of defective row address comparison circuits in response to the respective hit signal indicating that the prime row address matches the respective defective prime row address.

9. The apparatus of claim 1 , wherein, during the access operation, the first predecoder is configured to prevent the first threshold voltage compensation operation from being initiated on any respective redundant row of any of the first plurality of row sections in response to the respective hit signals of each of the first plurality of defective row address comparison circuits indicating a miss.

10. The apparatus of claim 1 , wherein, during the access operation, the first predecoder is configured to cause the second threshold voltage compensation operation to be initiated on a prime row of a third row section of the first plurality of row sections when the prime row of the third row section of the first plurality of row sections corresponds to the prime row address.

11. An apparatus comprising:
a first plurality of fuse latch and comparator circuits each associated with a particular row section of a first plurality of row sections and configured to store a respective defective row address, wherein individual ones of the first plurality of fuse latch and comparator circuits are each configured to, in response to a determination that a received prime row address matches the respective defective row address, provide a respective match signal;
a second plurality of fuse latch and comparator circuits each associated with a particular row section of a second plurality of row sections and configured to store a respective defective row address, wherein individual ones of the second plurality of fuse latch and comparator circuits are each configured to, in response to a determination that a received prime row address matches the respective defective row address, provide a respective match signal;
a logic tree configured to compare the respective match signals from the first of fuse latch and comparator circuits to provide a first fast hit signal and to compare the respective hit signals from the second plurality of fuse latch and comparator circuits to provide a second fast hit signal, wherein the logic tree is further configured to compare the first and second fast hit signals to provide a hit signal;
a first predecoder coupled to the first plurality of fuse latch and comparator circuits to receive the respective match signal and to receive the prime row address, wherein, in response to one of the respective match signal, cause a first threshold voltage compensation to be initiated on a first redundant row associated with the first fuse latch and comparator circuit, wherein, in response to a determination that the decoded prime row address targets a first prime row of the first plurality of row sections, cause a second threshold voltage compensation operation to be initiated on the first prime row, wherein, in response to the first or second fast hit signals being set, the first predecoder is configured to prevent an access operation associated with the first prime row from proceeding; and
a second predecoder coupled to the second plurality of fuse latch and comparator circuits and configured to receive the second match signal and to receive the prime row address, wherein, in response to the first match signal, cause a third threshold voltage compensation to be initiated on a second redundant row associated with the second fuse latch and comparator circuit, wherein, in response to a determination that the decoded prime row address targets a second prime row of the second plurality of row sections, cause a fourth threshold voltage compensation operation to be initiated on the second prime row, wherein at least one of the first or third threshold voltage compensation operations is at least partial

Assignees

• Micron Technology Inc

Inventors

• Rice Jacob
• Akamatsu Hiroshi

Classifications

• G11C29/84

  with improved access time or stability · CPC title

• G11C29/787

  using a fuse hierarchy · CPC title

• G11C16/3404

  Convergence or correction of memory cell threshold voltages; Repair or recovery of overerased or overprogrammed cells · CPC title

• G11C16/08 Primary

  Address circuits; Decoders; Word-line control circuits · CPC title

• G11C29/44

  Indication or identification of errors, e.g. for repair · CPC title