Apparatuses and methods for increased reliability row hammer counts

Patent metadata

Field	Value
Publication number	US-2024212738-A1
Application number	US-202318481134-A
Country	US
Kind code	A1
Filing date	Oct 4, 2023
Priority date	Dec 22, 2022
Publication date	Jun 27, 2024
Grant date	—

Abstract

Apparatuses and methods increased reliability row hammer counts. Each word line of a memory may have an associated count value, stored in memory cells of the word line. Information in memory cells may be prone to change, such as from neutron strike. A counter circuit may decrease the count value each time the word line is accessed, since a decreasing count will tend to overestimate accesses due to error. A count error correction circuit may check the count value against redundant information and correct the count value if there is an error. Decreasing counts and count error correction may be used together to further increase reliability.

First claim

What is claimed is:

1 . An apparatus comprising:
a word line intersecting a plurality of memory cells which are configured to store a count value; a first control circuit configured to receive the count value as part of an access operation on the word line and invert a logical state of the bits of the count value to generate an inverted count value; a count circuit configured to increase the inverted count value to generate an updated inverted count value; a second control circuit configured to receive the updated inverted count value and invert a logical state of the bits of the updated inverted count value to generate an updated count value, wherein the updated count value is written back to the plurality of memory cells.

2 . The apparatus of claim 1 , wherein the updated count value is decremented from the count value.

3 . The apparatus of claim 1 , wherein the count circuit is configured to provide an aggressor signal at an active level when the updated inverted count value exceeds a threshold; the apparatus further comprising:
an aggressor address register configured to store a row address associated with the word line responsive to aggressor signal at the active level.

4 . The apparatus of claim 3 , wherein the threshold is based on a maximum value of the count value.

5 . The apparatus of claim 3 , further comprising a refresh address generator configured to generate one or more refresh addresses based on the row address in the aggressor address register responsive to a targeted refresh operation.

6 . The apparatus of claim 1 , further comprising:
a second plurality of memory cells configured to store redundant information based on the count value; and a count error correction circuit configured to correct the count value based on the count value and the redundant information responsive to the access operation.

7 . A method comprising:
reading a count value from memory cells along a word line, wherein the count value is associated with a number of accesses to the word line; inverting the count value; increasing the inverted count value; inverting the increased inverted count value to generate an updated count value; writing the updated count value back to the memory cells; and determining if the word line is an aggressor row based on the updated count value.

8 . The method of claim 7 , further comprising:
accessing information in other memory cells along the word line; and reading the count value responsive to the accessing.

9 . The method of claim 7 , further comprising:
determining if a row address associated with the word line is an aggressor address based on the increased inverted count value; and storing the row address in an aggressor address register if the row address is an aggressor address.

10 . The method of claim 9 , further comprising:
refreshing one or more addresses based on the row address in the aggressor address register as part of a targeted refresh operation.

11 . The method of claim 7 , further comprising:
reading redundant information from extra memory cells along the word line, wherein the redundant information is based on the count value; and correcting the count value with a count error correction circuit based on the count value and the redundant information.

12 . An apparatus comprising:
a word line intersecting a plurality of memory cells which are configured to store a count value and redundant information, wherein the redundant information represents at least a portion of the bits of the count value; a count value correction circuit configured to receive the count value and the redundant information and to generate a corrected count value based on the count value and the redundant information; a counter circuit configured to update the corrected count value and determine if the word line is an aggressor based on the updated corrected count value, wherein the updated corrected count value is written back to the plurality of memory cells as the count value and the at least a portion of the bits of the corrected count value is written back to the plurality of memory cells as the redundant information.

13 . The apparatus of claim 12 , wherein the counter circuit is configured to identify the word line as an aggressor based on the corrected count value rolling over to an initial value.

14 . The apparatus of claim 12 , wherein responsive to the counter circuit identifying the word line as an aggressor, a row address associated with the word line is stored in an aggressor address register.

15 . The apparatus of claim 14 , further comprising a refresh address generator configured to generate one or more refresh address based on the row address in the aggressor address register responsive to a targeted refresh operation.

16 . The apparatus of claim 12 , wherein the count value correction circuit comprises a majority voting circuit configured to set a value of the corrected count value based on a majority of the values of the at least a portion of the count value and the redundant information.

17 . The apparatus of claim 12 , wherein the redundant information is one or more copies of a portion of the most significant bits of the count value.

18 . The apparatus of claim 12 , wherein the count value correction circuit is configured to receive the count value as part of an access operation to other memory cells intersecting the word line.

19 . The apparatus of claim 12 , further comprising:
a first control circuit configured to invert the corrected count value and provide the inverted count value to the counter circuit; and a second control circuit configured to receive the updated corrected count value from the counter circuit and provide an inverted updated corrected count value to the plurality of memory cells.

20 . A method comprising:
storing a count value and redundant information in memory cells along a word line; reading the count value and the redundant information responsive to an access operation on the word line; correcting the count value based on the count value and the redundant information; changing the corrected count value; writing the changed corrected count value as the count value and a portion of the changed corrected count value as the redundant information to the memory cells along the word line.

21 . The method of claim 20 , further comprising:
writing a portion of most significant bits of the changed corrected count value as the redundant information.

22 . The method of claim 20 , further comprising changing the corrected count value by decreasing the corrected count value.

23 . The method of claim 20 , further comprising determining if the word line is an aggressor based on the changed corrected count value.

24 . The method of claim 21 , further comprising refreshing one or more other word lines based on the word line as part of a targeted refresh operation if the word line is determined to be an aggressor.

25 . The method of claim 20 , further comprising:
comparing a bit of the count value to corresponding bits of the redundant information and correcting the count value based on a majority of the values of the bit and the corresponding bits.

Assignees

• Micron Technology Inc

Inventors

• Akamatsu Hiroshi
• He Yuan

Classifications

• G11C8/08

  Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines · CPC title

• G11C8/14

  Word line organisation; Word line lay-out · CPC title

• G11C11/40615 Primary

  Internal triggering or timing of refresh, e.g. hidden refresh, self refresh, pseudo-SRAMs · CPC title

• G11C11/408 Primary

  Address circuits · CPC title

• G11C29/52

  Protection of memory contents; Detection of errors in memory contents · CPC title