Boundary protection in memory

Patent metadata

Field	Value
Publication number	US-11615828-B2
Application number	US-202117524514-A
Country	US
Kind code	B2
Filing date	Nov 11, 2021
Priority date	Jul 9, 2020
Publication date	Mar 28, 2023
Grant date	Mar 28, 2023

Abstract

Apparatuses and methods related to power domain boundary protection in memory. A number of embodiments can include using a voltage detector to monitor a floating power supply voltage used to power a number of logic components while a memory device operates in a reduced power mode, and responsive to the voltage detector detecting that the floating power supply voltage reaches a threshold value while the memory device is in the reduced power mode, providing a control signal to protection logic to prevent a floating output signal driven from one or more of the logic components from being provided across a power domain boundary to one or more of a different number of logic components.

First claim

What is claimed is:

1. An apparatus, comprising:
a first number of components of a memory device, wherein the first number of components are powered by a first power supply voltage while the memory device operates in a first power mode and while the memory device operates in a second power mode; and
power mode circuitry configured to:
in association with the memory device switching from the first power mode to the second power mode, disconnect a second number of components of the memory device from the first power supply voltage such that a floated power supply voltage is provided to the second number of components;
monitor the floated power supply voltage while the memory device is in the second power mode; and
responsive to detecting that the floated power supply voltage meets a first criteria while the memory device is in the second power mode, provide a control signal to protection logic to prevent a floating output signal driven from one or more of the second number of components from being provided to one or more of the first number of components.

2. The apparatus of claim 1 , wherein the second number of components comprises sub-threshold current reduction circuit (SCRC) logic.

3. The apparatus of claim 2 , wherein the power mode circuitry is configured to, for floating output signals driven by the SCRC logic, utilize a single damper transistor per floating output signal to pull the floating output signal to a particular voltage.

4. The apparatus of claim 2 , wherein the second number of components comprises non-SCRC logic, and wherein the power mode circuitry is configured to, for floating output signals driven by the non-SCRC logic, utilize a NAND gate or a NOR gate as protection logic with a first input coupled to the floating output signal and a second input coupled to the control signal.

5. The apparatus of claim 1 , wherein the second number of components comprises latches storing fuse data that is lost when the memory device is in the second power mode.

6. The apparatus of claim 5 , wherein the power mode circuitry is configured to rebroadcast the fuse information to the latches while the memory device is exiting the second power mode.

7. The apparatus of claim 1 , wherein the first power supply voltage is an external supply voltage, and wherein the second power mode is a deep sleep mode.

8. The apparatus of claim 1 , wherein the power mode circuitry comprises:
a voltage detector powered by, and configured to monitor, the floated power supply voltage; and
a level shifter powered by the first supply voltage and configured to provide detection information to a power domain corresponding to the first number of components in association with the memory device entering the second power mode from the first power mode and in association with the memory device exiting the second power mode.

9. A method, comprising:
powering a first number of components of a memory device with a first power supply voltage while the memory device operates in a first power mode and while the memory device operates in a second power mode; and
providing a floated power supply voltage to a second number of components by disconnecting the second number of components from the first power supply voltage in association with the memory device switching from the first power mode to the second power mode;
monitoring the floated power supply voltage while the memory device is in the second power mode; and
responsive to detecting that the floated power supply voltage meets a first criteria while the memory device is in the second power mode, providing a control signal to protection logic to prevent a floating output signal driven from one or more of the second number of components from being provided to one or more of the first number of components.

10. The method of claim 9 , wherein the second number of components includes a sub-threshold current reduction circuitry (SCRC) driver, and wherein the method includes providing the floating output signal from the SCRC driver to a damper device of the protection logic.

11. The method of claim 10 , wherein the method includes providing the control signal to a gate of the clamper device.

12. The method of claim 9 , wherein the memory device comprises a memory array comprising a number of banks, and bank logic configured to provide control signals to the number of banks; and wherein the method includes:
responsive to detecting that the floated power supply voltage does not meet the first criteria while the memory device is in the second power mode, preventing the control signal from being provided to the protection logic; and
in association with the memory device returning to the first power mode from the second power mode:
reconnecting the floated power supply voltage to the first power supply voltage;
detecting when the floated power supply meets a second criteria; and
responsive to detecting that the floated power supply voltage meets the second criteria, disabling the protection logic.

13. The method of claim 9 , wherein the second number of components comprises SCRC logic and non-SCRC logic configured to drive signals to the first number of components.

14. The method of claim 13 , wherein the method includes connecting, via a plurality of switches of the power mode circuitry, a respective plurality of components of the second number of components to the first power supply voltage in association with returning from the second power mode to the first power mode.

15. The method of claim 14 , wherein the method includes:
disconnecting the respective plurality of components of the second number of components from the first power supply voltage in association with entering the second power mode from the first power mode; and
in association with the memory device returning from the second power mode to the first power mode, staggering enabling of the plurality of switches to reduce a peak current draw on the first power supply voltage.

16. A memory device, comprising:
a first number of components corresponding to a first power domain, the first number of components powered by a first power supply voltage while the memory device operates in a first power mode and while the memory device operates in a second power mode; and
a second number of components corresponding to a second power domain, the second number of components powered by a floating power supply voltage when the memory device is in the second power mode;
a voltage detector configured to monitor the floating power supply when the memory device is in the second power mode, wherein the voltage detector is powered by the floating power supply voltage; and
boundary protection logic configured to, responsive to a determination that the floating power supply voltage has met a particular criteria while the memory device is in the second power mode, prevent a floating output signal driven from one or more of the second number of components from being provided to one or more of the first number of components.

17. The memory device of claim 16 , wherein the second number of components are powered by the first power supply voltage when the memory device is in the first power mode, and wherein the memory device comprises a number of switches configured to disconnect the first power supply voltage from the second number of components in association with entering the second power mode.

18. The memory device of claim 17 , wherein the number of switches are configured to reconnect the first power supply voltage to the second number of components in association with returning f

Assignees

• Micron Technology Inc

Inventors

• Nam Ki-Jun
• Akamatsu Hiroshi
• Suzuki Takamasa
• Matsubara Yasushi

Classifications

• G06F11/3062

  where the monitored property is the power consumption (power management in a computing system G06F1/3203) · CPC title

• G11C11/2297 Primary

  Power supply circuits · CPC title

• G11C5/148

  Details of power up or power down circuits, standby circuits or recovery circuits · CPC title

• G06F11/3058

  Monitoring arrangements for monitoring environmental properties or parameters of the computing system or of the computing system component, e.g. monitoring of power, currents, temperature, humidity, position, vibrations (thermal management in cooling arrangements of a computing system G06F1/206) · CPC title

• G11C11/4074 Primary

  Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits · CPC title